mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-11 07:13:21 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Convert over this driver, using device tree to pass in the required information. The peripheral is still probed, just the number of GPIO banks and their offsets is in the device tree (previously this was a table in the driver). Signed-off-by: Simon Glass <sjg@chromium.org>
265 lines
7.4 KiB
C
265 lines
7.4 KiB
C
/*
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* Copyright (c) 2012 The Chromium OS Authors.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
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* through the PCI bus. Each PCI device has 256 bytes of configuration space,
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* consisting of a standard header and a device-specific set of registers. PCI
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* bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
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* other things). Within the PCI configuration space, the GPIOBASE register
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* tells us where in the device's I/O region we can find more registers to
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* actually access the GPIOs.
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*
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* PCI bus/device/function 0:1f:0 => PCI config registers
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* PCI config register "GPIOBASE"
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* PCI I/O space + [GPIOBASE] => start of GPIO registers
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* GPIO registers => gpio pin function, direction, value
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*
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*
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* Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
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* ICH versions have more, but the decoding the matrix that describes them is
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* absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
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* but they will ONLY work for certain unspecified chipsets because the offset
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* from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
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* reserved or subject to arcane restrictions.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <pci.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#define GPIO_PER_BANK 32
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/* Where in config space is the register that points to the GPIO registers? */
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#define PCI_CFG_GPIOBASE 0x48
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struct ich6_bank_priv {
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/* These are I/O addresses */
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uint32_t use_sel;
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uint32_t io_sel;
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uint32_t lvl;
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};
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static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
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{
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struct ich6_bank_platdata *plat = dev_get_platdata(dev);
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pci_dev_t pci_dev; /* handle for 0:1f:0 */
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u8 tmpbyte;
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u16 tmpword;
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u32 tmplong;
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u32 gpiobase;
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int offset;
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/* Where should it be? */
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pci_dev = PCI_BDF(0, 0x1f, 0);
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/* Is the device present? */
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pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword);
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if (tmpword != PCI_VENDOR_ID_INTEL) {
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debug("%s: wrong VendorID\n", __func__);
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return -ENODEV;
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}
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pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword);
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debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
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/*
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* We'd like to validate the Device ID too, but pretty much any
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* value is either a) correct with slight differences, or b)
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* correct but undocumented. We'll have to check a bunch of other
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* things instead...
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*/
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/* I/O should already be enabled (it's a RO bit). */
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pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword);
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if (!(tmpword & PCI_COMMAND_IO)) {
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debug("%s: device IO not enabled\n", __func__);
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return -ENODEV;
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}
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/* Header Type must be normal (bits 6-0 only; see spec.) */
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pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte);
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if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
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debug("%s: invalid Header type\n", __func__);
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return -ENODEV;
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}
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/* Base Class must be a bridge device */
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pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte);
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if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
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debug("%s: invalid class\n", __func__);
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return -ENODEV;
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}
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/* Sub Class must be ISA */
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pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte);
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if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
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debug("%s: invalid subclass\n", __func__);
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return -ENODEV;
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}
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/* Programming Interface must be 0x00 (no others exist) */
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pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte);
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if (tmpbyte != 0x00) {
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debug("%s: invalid interface type\n", __func__);
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return -ENODEV;
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}
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/*
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* GPIOBASE moved to its current offset with ICH6, but prior to
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* that it was unused (or undocumented). Check that it looks
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* okay: not all ones or zeros, and mapped to I/O space (bit 0).
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*/
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pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong);
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if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
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!(tmplong & 0x00000001)) {
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debug("%s: unexpected GPIOBASE value\n", __func__);
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return -ENODEV;
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}
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/*
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* Okay, I guess we're looking at the right device. The actual
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* GPIO registers are in the PCI device's I/O space, starting
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* at the offset that we just read. Bit 0 indicates that it's
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* an I/O address, not a memory address, so mask that off.
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*/
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gpiobase = tmplong & 0xfffffffe;
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offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
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if (offset == -1) {
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debug("%s: Invalid register offset %d\n", __func__, offset);
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return -EINVAL;
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}
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plat->base_addr = gpiobase + offset;
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plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
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"bank-name", NULL);
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return 0;
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}
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int ich6_gpio_probe(struct udevice *dev)
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{
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struct ich6_bank_platdata *plat = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev->uclass_priv;
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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bank->use_sel = plat->base_addr;
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bank->io_sel = plat->base_addr + 4;
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bank->lvl = plat->base_addr + 8;
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return 0;
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}
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int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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/*
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* Make sure that the GPIO pin we want isn't already in use for some
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* built-in hardware function. We have to check this for every
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* requested pin.
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*/
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tmplong = inl(bank->use_sel);
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if (!(tmplong & (1UL << offset))) {
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debug("%s: gpio %d is reserved for internal use\n", __func__,
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offset);
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return -EPERM;
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}
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return 0;
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}
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static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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tmplong = inl(bank->io_sel);
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tmplong |= (1UL << offset);
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outl(bank->io_sel, tmplong);
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return 0;
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}
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static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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tmplong = inl(bank->io_sel);
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tmplong &= ~(1UL << offset);
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outl(bank->io_sel, tmplong);
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return 0;
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}
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static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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int r;
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tmplong = inl(bank->lvl);
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r = (tmplong & (1UL << offset)) ? 1 : 0;
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return r;
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}
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static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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tmplong = inl(bank->lvl);
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if (value)
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tmplong |= (1UL << offset);
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else
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tmplong &= ~(1UL << offset);
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outl(bank->lvl, tmplong);
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return 0;
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}
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static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 mask = 1UL << offset;
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if (!(inl(bank->use_sel) & mask))
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return GPIOF_FUNC;
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if (inl(bank->io_sel) & mask)
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return GPIOF_INPUT;
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else
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return GPIOF_OUTPUT;
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}
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static const struct dm_gpio_ops gpio_ich6_ops = {
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.request = ich6_gpio_request,
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.direction_input = ich6_gpio_direction_input,
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.direction_output = ich6_gpio_direction_output,
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.get_value = ich6_gpio_get_value,
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.set_value = ich6_gpio_set_value,
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.get_function = ich6_gpio_get_function,
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};
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static const struct udevice_id intel_ich6_gpio_ids[] = {
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{ .compatible = "intel,ich6-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_ich6) = {
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.name = "gpio_ich6",
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.id = UCLASS_GPIO,
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.of_match = intel_ich6_gpio_ids,
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.ops = &gpio_ich6_ops,
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.ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
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.probe = ich6_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
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.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
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};
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