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https://github.com/brain-hackers/u-boot-brain
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This patch modifies PL bitstream loading sequence as per latest Xilfpga which supports all variants of bitstream images generated from vivado and from bootgen. With this new change in Xilfpga, uboot doesn't need to validate and swap bitstream as it will be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting PMUFW version before skipping the validation and swap sequence as there can be old PMUFW which doesn't supports this feature. In this case, driver uses old way of PL bitstream loading sequence. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
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| .. | ||
| ACEX1K.c | ||
| altera.c | ||
| cyclon2.c | ||
| fpga.c | ||
| ivm_core.c | ||
| Kconfig | ||
| lattice.c | ||
| Makefile | ||
| socfpga_arria10.c | ||
| socfpga_gen5.c | ||
| socfpga.c | ||
| spartan2.c | ||
| spartan3.c | ||
| stratixII.c | ||
| stratixv.c | ||
| virtex2.c | ||
| xilinx.c | ||
| zynqmppl.c | ||
| zynqpl.c | ||