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![Jagan Teki](/assets/img/avatar_default.png)
Add IPUv3 framebuffer support for Engicam i.CoreM6 qdl board. Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
580 lines
15 KiB
C
580 lines
15 KiB
C
/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/video.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart4_pads[] = {
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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#ifdef CONFIG_NAND_MXS
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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iomux_v3_cfg_t gpmi_pads[] = {
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IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
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IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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SETUP_IOMUX_PADS(gpmi_pads);
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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#if defined(CONFIG_VIDEO_IPUV3)
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static iomux_v3_cfg_t const rgb_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
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IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
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IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
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IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
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IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
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IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
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IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
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IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
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IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
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IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
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IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
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IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
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IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
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IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
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IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
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IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
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IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
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IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
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IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
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IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
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};
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static void enable_rgb(struct display_info_t const *dev)
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{
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SETUP_IOMUX_PADS(rgb_pads);
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}
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struct display_info_t const displays[] = {
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{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.detect = NULL,
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.enable = enable_rgb,
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.mode = {
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.name = "Amp-WD",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30000,
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.left_margin = 30,
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.right_margin = 30,
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.upper_margin = 5,
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.lower_margin = 5,
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.hsync_len = 64,
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.vsync_len = 20,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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}
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},
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};
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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/* Turn on LDB0,IPU,IPU DI0 clocks */
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reg = __raw_readl(&mxc_ccm->CCGR3);
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reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
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writel(reg, &mxc_ccm->CCGR3);
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/* set LDB0, LDB1 clk select to 011/011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
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MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
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(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
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IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
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IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
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IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
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IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
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(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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int board_early_init_f(void)
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{
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SETUP_IOMUX_PADS(uart4_pads);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <libfdt.h>
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#include <spl.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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/* MMC board initialization is needed till adding DM support in SPL */
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#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
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};
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC1_BASE_ADDR, 0, 4},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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SETUP_IOMUX_PADS(usdhc1_pads);
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gpio_direction_input(USDHC1_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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default:
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printf("Warning - USDHC%d controller not supporting\n",
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i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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#endif
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/*
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* Driving strength:
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* 0x30 == 40 Ohm
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* 0x28 == 48 Ohm
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*/
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#define IMX6DQ_DRIVE_STRENGTH 0x30
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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.dram_sdqs0 = 0x28,
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.dram_sdqs1 = 0x28,
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.dram_sdqs2 = 0x28,
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.dram_sdqs3 = 0x28,
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.dram_sdqs4 = 0x28,
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.dram_sdqs5 = 0x28,
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.dram_sdqs6 = 0x28,
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.dram_sdqs7 = 0x28,
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.dram_dqm0 = 0x28,
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.dram_dqm1 = 0x28,
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.dram_dqm2 = 0x28,
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.dram_dqm3 = 0x28,
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.dram_dqm4 = 0x28,
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.dram_dqm5 = 0x28,
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.dram_dqm6 = 0x28,
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.dram_dqm7 = 0x28,
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.dram_cas = 0x30,
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.dram_ras = 0x30,
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.dram_sdclk_0 = 0x30,
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.dram_sdclk_1 = 0x30,
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.dram_reset = 0x30,
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.dram_sdcke0 = 0x3000,
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.dram_sdcke1 = 0x3000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x30,
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.dram_sdodt1 = 0x30,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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.grp_b0ds = 0x30,
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.grp_b1ds = 0x30,
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.grp_b2ds = 0x30,
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.grp_b3ds = 0x30,
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.grp_b4ds = 0x30,
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.grp_b5ds = 0x30,
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.grp_b6ds = 0x30,
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.grp_b7ds = 0x30,
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.grp_addds = 0x30,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ctlds = 0x30,
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.grp_ddr_type = 0x000c0000,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = 0x30,
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.dram_sdclk_1 = 0x30,
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.dram_cas = 0x30,
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.dram_ras = 0x30,
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.dram_reset = 0x30,
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.dram_sdcke0 = 0x30,
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.dram_sdcke1 = 0x30,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x30,
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.dram_sdodt1 = 0x30,
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.dram_sdqs0 = 0x28,
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.dram_sdqs1 = 0x28,
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.dram_sdqs2 = 0x28,
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.dram_sdqs3 = 0x28,
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.dram_sdqs4 = 0x28,
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.dram_sdqs5 = 0x28,
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.dram_sdqs6 = 0x28,
|
|
.dram_sdqs7 = 0x28,
|
|
.dram_dqm0 = 0x28,
|
|
.dram_dqm1 = 0x28,
|
|
.dram_dqm2 = 0x28,
|
|
.dram_dqm3 = 0x28,
|
|
.dram_dqm4 = 0x28,
|
|
.dram_dqm5 = 0x28,
|
|
.dram_dqm6 = 0x28,
|
|
.dram_dqm7 = 0x28,
|
|
};
|
|
|
|
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
|
|
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
|
|
.grp_ddr_type = 0x000c0000,
|
|
.grp_ddrmode_ctl = 0x00020000,
|
|
.grp_ddrpke = 0x00000000,
|
|
.grp_addds = 0x30,
|
|
.grp_ctlds = 0x30,
|
|
.grp_ddrmode = 0x00020000,
|
|
.grp_b0ds = 0x28,
|
|
.grp_b1ds = 0x28,
|
|
.grp_b2ds = 0x28,
|
|
.grp_b3ds = 0x28,
|
|
.grp_b4ds = 0x28,
|
|
.grp_b5ds = 0x28,
|
|
.grp_b6ds = 0x28,
|
|
.grp_b7ds = 0x28,
|
|
};
|
|
|
|
/* mt41j256 */
|
|
static struct mx6_ddr3_cfg mt41j256 = {
|
|
.mem_speed = 1066,
|
|
.density = 2,
|
|
.width = 16,
|
|
.banks = 8,
|
|
.rowaddr = 13,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
.SRT = 0,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
|
|
.p0_mpwldectrl0 = 0x000E0009,
|
|
.p0_mpwldectrl1 = 0x0018000E,
|
|
.p1_mpwldectrl0 = 0x00000007,
|
|
.p1_mpwldectrl1 = 0x00000000,
|
|
.p0_mpdgctrl0 = 0x43280334,
|
|
.p0_mpdgctrl1 = 0x031C0314,
|
|
.p1_mpdgctrl0 = 0x4318031C,
|
|
.p1_mpdgctrl1 = 0x030C0258,
|
|
.p0_mprddlctl = 0x3E343A40,
|
|
.p1_mprddlctl = 0x383C3844,
|
|
.p0_mpwrdlctl = 0x40404440,
|
|
.p1_mpwrdlctl = 0x4C3E4446,
|
|
};
|
|
|
|
/* DDR 64bit */
|
|
static struct mx6_ddr_sysinfo mem_q = {
|
|
.ddr_type = DDR_TYPE_DDR3,
|
|
.dsize = 2,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 2,
|
|
.rtt_wr = 2,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
|
|
.p0_mpwldectrl0 = 0x001F0024,
|
|
.p0_mpwldectrl1 = 0x00110018,
|
|
.p1_mpwldectrl0 = 0x001F0024,
|
|
.p1_mpwldectrl1 = 0x00110018,
|
|
.p0_mpdgctrl0 = 0x4230022C,
|
|
.p0_mpdgctrl1 = 0x02180220,
|
|
.p1_mpdgctrl0 = 0x42440248,
|
|
.p1_mpdgctrl1 = 0x02300238,
|
|
.p0_mprddlctl = 0x44444A48,
|
|
.p1_mprddlctl = 0x46484A42,
|
|
.p0_mpwrdlctl = 0x38383234,
|
|
.p1_mpwrdlctl = 0x3C34362E,
|
|
};
|
|
|
|
/* DDR 64bit 1GB */
|
|
static struct mx6_ddr_sysinfo mem_dl = {
|
|
.dsize = 2,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 1,
|
|
.rtt_wr = 1,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
};
|
|
|
|
/* DDR 32bit 512MB */
|
|
static struct mx6_ddr_sysinfo mem_s = {
|
|
.dsize = 1,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 1,
|
|
.rtt_wr = 1,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
};
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0x00003F3F, &ccm->CCGR0);
|
|
writel(0x0030FC00, &ccm->CCGR1);
|
|
writel(0x000FC000, &ccm->CCGR2);
|
|
writel(0x3F300000, &ccm->CCGR3);
|
|
writel(0xFF00F300, &ccm->CCGR4);
|
|
writel(0x0F0000C3, &ccm->CCGR5);
|
|
writel(0x000003CC, &ccm->CCGR6);
|
|
}
|
|
|
|
static void gpr_init(void)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
/* enable AXI cache for VDOA/VPU/IPU */
|
|
writel(0xF00000CF, &iomux->gpr[4]);
|
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
|
writel(0x007F007F, &iomux->gpr[6]);
|
|
writel(0x007F007F, &iomux->gpr[7]);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
if (is_mx6solo()) {
|
|
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
|
|
} else if (is_mx6dl()) {
|
|
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
|
|
} else if (is_mx6dq()) {
|
|
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
|
|
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
|
|
}
|
|
|
|
udelay(100);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
ccgr_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
gpr_init();
|
|
|
|
/* iomux */
|
|
board_early_init_f();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
#endif
|