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https://github.com/brain-hackers/u-boot-brain
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6024467bcc
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2016 Andreas Färber
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*/
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#ifndef __CONFIG_RK3368_COMMON_H
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#define __CONFIG_RK3368_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#include <asm/arch-rockchip/hardware.h>
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#include <linux/sizes.h>
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#define CONFIG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xff000000
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
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#define COUNTER_FREQUENCY 24000000
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#define CONFIG_IRAM_BASE 0xff8c0000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00280000
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#define CONFIG_SPL_MAX_SIZE 0x40000
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#define CONFIG_SPL_BSS_START_ADDR 0x400000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
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#define CONFIG_SPL_STACK 0x00188000
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00500000\0" \
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"pxefile_addr_r=0x00600000\0" \
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"fdt_addr_r=0x5600000\0" \
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"kernel_addr_r=0x280000\0" \
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"ramdisk_addr_r=0x5bf0000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
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ENV_MEM_LAYOUT_SETTINGS \
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BOOTENV
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#endif
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#endif
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