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https://github.com/brain-hackers/u-boot-brain
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89083346d0
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
126 lines
4.2 KiB
C
126 lines
4.2 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _SPARTAN3_H_
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#define _SPARTAN3_H_
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#include <xilinx.h>
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extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size );
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extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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extern int Spartan3_info( Xilinx_desc *desc );
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/* Slave Parallel Implementation function table */
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_init_fn init;
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Xilinx_err_fn err;
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Xilinx_done_fn done;
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Xilinx_clk_fn clk;
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Xilinx_cs_fn cs;
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Xilinx_wr_fn wr;
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Xilinx_rdata_fn rdata;
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Xilinx_wdata_fn wdata;
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Xilinx_busy_fn busy;
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Xilinx_abort_fn abort;
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Xilinx_post_fn post;
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} Xilinx_Spartan3_Slave_Parallel_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_clk_fn clk;
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Xilinx_init_fn init;
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Xilinx_done_fn done;
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Xilinx_wr_fn wr;
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Xilinx_post_fn post;
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Xilinx_bwr_fn bwr; /* block write function */
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} Xilinx_Spartan3_Slave_Serial_fns;
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/* Device Image Sizes
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*********************************************************************/
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/* Spartan-III (1.2V) */
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#define XILINX_XC3S50_SIZE 439264/8
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#define XILINX_XC3S200_SIZE 1047616/8
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#define XILINX_XC3S400_SIZE 1699136/8
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#define XILINX_XC3S1000_SIZE 3223488/8
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#define XILINX_XC3S1500_SIZE 5214784/8
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#define XILINX_XC3S2000_SIZE 7673024/8
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#define XILINX_XC3S4000_SIZE 11316864/8
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#define XILINX_XC3S5000_SIZE 13271936/8
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/* Spartan-3E (v3.4) */
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#define XILINX_XC3S100E_SIZE 581344/8
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#define XILINX_XC3S250E_SIZE 1353728/8
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#define XILINX_XC3S500E_SIZE 2270208/8
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#define XILINX_XC3S1200E_SIZE 3841184/8
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#define XILINX_XC3S1600E_SIZE 5969696/8
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/* Descriptor Macros
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*********************************************************************/
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/* Spartan-III devices */
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#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
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#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
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#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
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#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
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#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
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#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
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#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
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#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
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/* Spartan-3E devices */
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#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
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#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
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#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
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#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
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#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
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#endif /* _SPARTAN3_H_ */
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