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fba725f410
This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.
One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).
Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping
support in the DP83867 TI's PHY driver") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
31 lines
1.1 KiB
Plaintext
31 lines
1.1 KiB
Plaintext
* Texas Instruments - dp83867 Giga bit ethernet phy
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values
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- enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
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compensate for the board being designed with the lanes swapped.
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- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
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TX/RX lanes.
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Default child nodes are standard Ethernet PHY device
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nodes as described in doc/devicetree/bindings/net/ethernet.txt
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Example:
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ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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enet-phy-lane-no-swap;
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};
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Datasheet can be found:
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http://www.ti.com/product/DP83867IR/datasheet
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