mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 03:49:43 +09:00
a09b9b68d4
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#if defined(CONFIG_FSL_CORENET)
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#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
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#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
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#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#elif defined(CONFIG_MPC85xx)
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#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
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#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
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#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#elif defined(CONFIG_MPC86xx)
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#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
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#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
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#define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
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(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
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#else
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#error "No defines for DEVDISR_SRIO"
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#endif
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void srio_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
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int srio1_used = 0, srio2_used = 0;
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if (is_serdes_configured(SRIO1)) {
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set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
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law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
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LAW_TRGT_IF_RIO_1);
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srio1_used = 1;
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printf("SRIO1: enabled\n");
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} else {
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printf("SRIO1: disabled\n");
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}
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#ifdef CONFIG_SRIO2
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if (is_serdes_configured(SRIO2)) {
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set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
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law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
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LAW_TRGT_IF_RIO_2);
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srio2_used = 1;
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printf("SRIO2: enabled\n");
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} else {
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printf("SRIO2: disabled\n");
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}
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#endif
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#ifdef CONFIG_FSL_CORENET
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/* On FSL_CORENET devices we can disable individual ports */
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if (!srio1_used)
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
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if (!srio2_used)
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
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#endif
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/* neither port is used - disable everything */
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if (!srio1_used && !srio2_used) {
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setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
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setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
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setbits_be32(&gur->devdisr, _DEVDISR_RMU);
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}
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}
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