mirror of
https://github.com/brain-hackers/u-boot-brain
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fb855f43a1
Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* We run cpu_init_early_f in AS = 1 */
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void cpu_init_early_f(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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int i;
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/*
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* Clear initial global data
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* we don't use memset so we can share this code with NAND_SPL
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*/
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for (i = 0; i < sizeof(gd_t); i++)
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((char *)gd)[i] = 0;
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
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write_tlb(mas0, mas1, mas2, mas3, mas7);
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/*
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* Work Around for IFC Erratum A-003549. This issue is P1010
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* specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
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* Hence specifically selecting CS3.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
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#endif
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init_laws();
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invalidate_tlb(1);
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init_tlbs();
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}
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