mirror of
https://github.com/brain-hackers/u-boot-brain
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65dd74a674
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_CAR_ADDR 0xff7e0000
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#define CONFIG_SYS_CAR_SIZE (128 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
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#define CONFIG_SYS_X86_START16 0xfffff800
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_X86_RESET_VECTOR
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#define CONFIG_NR_DRAM_BANKS 8
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#define CONFIG_X86_MRC_START 0xfffa0000
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#define CONFIG_CACHE_MRC_SIZE_KB 512
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#define CONFIG_COREBOOT_SERIAL
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#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
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/*
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* These common x86 features are not yet supported, but are added in
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* follow-on patches in this series. Add undefs here to avoid every patch
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* having to put things back into x86-common.h
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*/
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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#undef CONFIG_ICH_SPI
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#undef CONFIG_SPI
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#undef CONFIG_CMD_SPI
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#undef CONFIG_CMD_SF
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#undef CONFIG_USB_EHCI
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#undef CONFIG_CMD_USB
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#undef CONFIG_CMD_SCSI
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#define CONFIG_PCI_MEM_BUS 0xe0000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_PREF_BUS 0xd0000000
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#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
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#define CONFIG_PCI_PREF_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x1000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0xefff
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
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"stdout=vga,serial\0" \
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"stderr=vga,serial\0"
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#endif /* __CONFIG_H */
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