mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
326 lines
9.4 KiB
C
326 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TI PHY drivers
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*
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*/
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#include <common.h>
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#include <phy.h>
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#include <linux/compat.h>
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#include <malloc.h>
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#include <fdtdec.h>
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#include <dm.h>
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#include <dt-bindings/net/ti-dp83867.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* TI DP83867 */
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#define DP83867_DEVADDR 0x1f
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#define MII_DP83867_PHYCTRL 0x10
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#define MII_DP83867_MICR 0x12
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#define MII_DP83867_CFG2 0x14
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#define MII_DP83867_BISCR 0x16
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#define DP83867_CTRL 0x1f
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/* Extended Registers */
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#define DP83867_RGMIICTL 0x0032
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#define DP83867_RGMIIDCTL 0x0086
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#define DP83867_IO_MUX_CFG 0x0170
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#define DP83867_SW_RESET BIT(15)
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#define DP83867_SW_RESTART BIT(14)
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/* MICR Interrupt bits */
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#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
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#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
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#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
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#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
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#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
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#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
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#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
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#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
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#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
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#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
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#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
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#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
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/* RGMIICTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
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#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
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#define DP83867_MDI_CROSSOVER 5
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#define DP83867_MDI_CROSSOVER_AUTO 2
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#define DP83867_MDI_CROSSOVER_MDIX 2
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#define DP83867_PHYCTRL_SGMIIEN 0x0800
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#define DP83867_PHYCTRL_RXFIFO_SHIFT 12
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#define DP83867_PHYCTRL_TXFIFO_SHIFT 14
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/* RGMIIDCTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
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/* CFG2 bits */
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#define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
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#define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
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#define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
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#define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
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#define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
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#define MII_DP83867_CFG2_MASK 0x003F
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#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
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#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
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/* MMD Access Control register fields */
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#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
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#define MII_MMD_CTRL_ADDR 0x0000 /* Address */
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#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
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#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
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#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
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/* User setting - can be taken from DTS */
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#define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS
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#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
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#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
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/* IO_MUX_CFG bits */
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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struct dp83867_private {
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int rx_id_delay;
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int tx_id_delay;
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int fifo_depth;
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int io_impedance;
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};
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/**
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* phy_read_mmd_indirect - reads data from the MMD registers
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* @phydev: The PHY device bus
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* @prtad: MMD Address
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* @devad: MMD DEVAD
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* @addr: PHY address on the MII bus
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*
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* Description: it reads data from the MMD registers (clause 22 to access to
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* clause 45) of the specified phy address.
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* To read these registers we have:
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* 1) Write reg 13 // DEVAD
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* 2) Write reg 14 // MMD Address
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* 3) Write reg 13 // MMD Data Command for MMD DEVAD
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* 3) Read reg 14 // Read MMD data
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*/
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int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
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int devad, int addr)
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{
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int value = -1;
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/* Write the desired MMD Devad */
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phy_write(phydev, addr, MII_MMD_CTRL, devad);
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/* Write the desired MMD register address */
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phy_write(phydev, addr, MII_MMD_DATA, prtad);
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/* Select the Function : DATA with no post increment */
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phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
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/* Read the content of the MMD's selected register */
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value = phy_read(phydev, addr, MII_MMD_DATA);
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return value;
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}
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/**
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* phy_write_mmd_indirect - writes data to the MMD registers
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* @phydev: The PHY device
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* @prtad: MMD Address
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* @devad: MMD DEVAD
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* @addr: PHY address on the MII bus
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* @data: data to write in the MMD register
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*
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* Description: Write data from the MMD registers of the specified
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* phy address.
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* To write these registers we have:
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* 1) Write reg 13 // DEVAD
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* 2) Write reg 14 // MMD Address
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* 3) Write reg 13 // MMD Data Command for MMD DEVAD
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* 3) Write reg 14 // Write MMD data
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*/
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void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
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int devad, int addr, u32 data)
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{
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/* Write the desired MMD Devad */
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phy_write(phydev, addr, MII_MMD_CTRL, devad);
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/* Write the desired MMD register address */
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phy_write(phydev, addr, MII_MMD_DATA, prtad);
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/* Select the Function : DATA with no post increment */
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phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
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/* Write the data into MMD's selected register */
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phy_write(phydev, addr, MII_MMD_DATA, data);
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}
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#if defined(CONFIG_DM_ETH)
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/**
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* dp83867_data_init - Convenience function for setting PHY specific data
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*
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* @phydev: the phy_device struct
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*/
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static int dp83867_of_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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struct udevice *dev = phydev->dev;
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int node = dev_of_offset(dev);
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const void *fdt = gd->fdt_blob;
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if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
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else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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else
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dp83867->io_impedance = -EINVAL;
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dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"ti,rx-internal-delay", -1);
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dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"ti,tx-internal-delay", -1);
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dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"ti,fifo-depth", -1);
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return 0;
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}
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#else
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static int dp83867_of_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
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dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
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dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
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dp83867->io_impedance = -EINVAL;
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return 0;
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}
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#endif
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static int dp83867_config(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867;
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unsigned int val, delay, cfg2;
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int ret;
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if (!phydev->priv) {
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dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
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if (!dp83867)
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return -ENOMEM;
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phydev->priv = dp83867;
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ret = dp83867_of_init(phydev);
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if (ret)
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goto err_out;
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} else {
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dp83867 = (struct dp83867_private *)phydev->priv;
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}
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/* Restart the PHY. */
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val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
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phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
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val | DP83867_SW_RESTART);
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if (phy_interface_is_rgmii(phydev)) {
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
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(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
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(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
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if (ret)
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goto err_out;
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} else if (phy_interface_is_sgmii(phydev)) {
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
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(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
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cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
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cfg2 &= MII_DP83867_CFG2_MASK;
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cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
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MII_DP83867_CFG2_SGMII_AUTONEGEN |
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MII_DP83867_CFG2_SPEEDOPT_ENH |
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MII_DP83867_CFG2_SPEEDOPT_CNT |
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MII_DP83867_CFG2_SPEEDOPT_INTLOW);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
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phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
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DP83867_DEVADDR, phydev->addr, 0x0);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
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DP83867_PHYCTRL_SGMIIEN |
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(DP83867_MDI_CROSSOVER_MDIX <<
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DP83867_MDI_CROSSOVER) |
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(dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
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(dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
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phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
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}
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if (phy_interface_is_rgmii(phydev)) {
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val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
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DP83867_DEVADDR, phydev->addr);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
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DP83867_RGMII_RX_CLK_DELAY_EN);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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val |= DP83867_RGMII_TX_CLK_DELAY_EN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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val |= DP83867_RGMII_RX_CLK_DELAY_EN;
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phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
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DP83867_DEVADDR, phydev->addr, val);
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delay = (dp83867->rx_id_delay |
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(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
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phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
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DP83867_DEVADDR, phydev->addr, delay);
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if (dp83867->io_impedance >= 0) {
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val = phy_read_mmd_indirect(phydev,
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DP83867_IO_MUX_CFG,
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DP83867_DEVADDR,
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phydev->addr);
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val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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val |= dp83867->io_impedance &
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DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
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DP83867_DEVADDR, phydev->addr,
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val);
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}
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}
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genphy_config_aneg(phydev);
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return 0;
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err_out:
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kfree(dp83867);
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return ret;
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}
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static struct phy_driver DP83867_driver = {
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.name = "TI DP83867",
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.uid = 0x2000a231,
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.mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &dp83867_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_ti_init(void)
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{
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phy_register(&DP83867_driver);
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return 0;
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}
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