Brad Kim fb33eaa3a2 riscv: fix the wrong swap value register ... Not s2 register, t1 register is correct Fortunately, it works because t1 register has a garbage value Signed-off-by: Brad Kim <brad.kim@semifive.com> Reviewed-by: Lukas Auer <lukas@auer.io> Reviewed-by: Leo Liang <ycliang@andestech.com>		2020-12-14 15:16:34 +08:00
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cpu	riscv: fix the wrong swap value register	2020-12-14 15:16:34 +08:00
dts	riscv: fu540: dts: Correct reg size of clint node	2020-10-26 10:01:37 +08:00
include/asm	riscv: Use a valid bit to ignore already-pending IPIs	2020-09-30 08:54:52 +08:00
lib	riscv: Move timer portions of SiFive CLINT to drivers/timer	2020-10-26 10:01:28 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: Move Andes PLMT driver to drivers/timer	2020-10-26 10:01:28 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00