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https://github.com/brain-hackers/u-boot-brain
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0c0d9b708b
For files like the drivers/serial/serial.c, it must include the platform file, as the CONFIG_SYS_NS16550_COM1 must reference to the definition in the platform definition files. Include the platform definition file in the config file, so that it would decouple the dependence for the driver files. Signed-off-by: Lei Wen <leiwen@marvell.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pantheon.h>
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#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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#define L2C_RAM_SEL (1<<4)
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int arch_cpu_init(void)
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{
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u32 val;
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struct panthcpu_registers *cpuregs =
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(struct panthcpu_registers*) PANTHEON_CPU_BASE;
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struct panthapb_registers *apbclkres =
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(struct panthapb_registers*) PANTHEON_APBC_BASE;
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struct panthmpmu_registers *mpmu =
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(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
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/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
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val = readl(&cpuregs->cpu_conf);
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val = val | SET_MRVL_ID;
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writel(val, &cpuregs->cpu_conf);
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/* Turn on clock gating (PMUM_CCGR) */
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writel(0xFFFFFFFF, &mpmu->ccgr);
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/* Turn on clock gating (PMUM_ACGR) */
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writel(0xFFFFFFFF, &mpmu->acgr);
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/* Turn on uart2 clock */
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writel(UARTCLK14745KHZ, &apbclkres->uart0);
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/* Enable GPIO clock */
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writel(APBC_APBCLK, &apbclkres->gpio);
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#ifdef CONFIG_I2C_MV
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/* Enable I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
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writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
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#endif
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icache_enable();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 id;
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struct panthcpu_registers *cpuregs =
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(struct panthcpu_registers*) PANTHEON_CPU_BASE;
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id = readl(&cpuregs->chip_id);
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printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
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return 0;
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}
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#endif
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#ifdef CONFIG_I2C_MV
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void i2c_clk_enable(void)
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{
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}
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#endif
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