mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
fb05f0b02b
As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense. This also describes the exact flash location where the u-boot.rom should be programmed in the documentation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
40 lines
944 B
Plaintext
40 lines
944 B
Plaintext
CONFIG_X86=y
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CONFIG_SYS_TEXT_BASE=0xFFE00000
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CONFIG_VENDOR_INTEL=y
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CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
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CONFIG_TARGET_COUGARCANYON2=y
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# CONFIG_HAVE_INTEL_ME is not set
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# CONFIG_ENABLE_MRC_CACHE is not set
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_HUSH_PARSER=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_PART=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_MAC_PARTITION=y
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CONFIG_ISO_PARTITION=y
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CONFIG_EFI_PARTITION=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_KEYBOARD=y
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# CONFIG_VIDEO_VESA is not set
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