mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Check whether a display device is in use before using it. Add a comment as to why two displays cannot currently be used at the same time. This allows us to remove the device-tree change that disables vopb on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
367 lines
9.8 KiB
C
367 lines
9.8 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <video.h>
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#include <asm/gpio.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/edp_rk3288.h>
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#include <asm/arch/hdmi_rk3288.h>
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#include <asm/arch/vop_rk3288.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk_vop_priv {
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struct rk3288_vop *regs;
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struct rk3288_grf *grf;
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};
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void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
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int fb_bits_per_pixel, const struct display_timing *edid)
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{
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u32 lb_mode;
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u32 rgb_mode;
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u32 hactive = edid->hactive.typ;
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u32 vactive = edid->vactive.typ;
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writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
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®s->win0_act_info);
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writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
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V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
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®s->win0_dsp_st);
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writel(V_DSP_WIDTH(hactive - 1) |
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V_DSP_HEIGHT(vactive - 1),
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®s->win0_dsp_info);
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clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
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V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
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switch (fb_bits_per_pixel) {
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case 16:
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rgb_mode = RGB565;
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writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir);
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break;
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case 24:
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rgb_mode = RGB888;
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writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir);
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break;
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case 32:
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default:
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rgb_mode = ARGB8888;
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writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir);
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break;
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}
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if (hactive > 2560)
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lb_mode = LB_RGB_3840X2;
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else if (hactive > 1920)
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lb_mode = LB_RGB_2560X4;
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else if (hactive > 1280)
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lb_mode = LB_RGB_1920X5;
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else
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lb_mode = LB_RGB_1280X8;
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clrsetbits_le32(®s->win0_ctrl0,
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M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
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V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
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V_WIN0_EN(1));
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writel(fbbase, ®s->win0_yrgb_mst);
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writel(0x01, ®s->reg_cfg_done); /* enable reg config */
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}
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void rkvop_mode_set(struct rk3288_vop *regs,
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const struct display_timing *edid, enum vop_modes mode)
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{
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u32 hactive = edid->hactive.typ;
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u32 vactive = edid->vactive.typ;
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u32 hsync_len = edid->hsync_len.typ;
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u32 hback_porch = edid->hback_porch.typ;
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u32 vsync_len = edid->vsync_len.typ;
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u32 vback_porch = edid->vback_porch.typ;
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u32 hfront_porch = edid->hfront_porch.typ;
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u32 vfront_porch = edid->vfront_porch.typ;
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uint flags;
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int mode_flags;
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switch (mode) {
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case VOP_MODE_HDMI:
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clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
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V_HDMI_OUT_EN(1));
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break;
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case VOP_MODE_EDP:
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default:
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clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
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V_EDP_OUT_EN(1));
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break;
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case VOP_MODE_LVDS:
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clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
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V_RGB_OUT_EN(1));
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break;
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}
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if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
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/* RGBaaa */
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mode_flags = 15;
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else
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/* RGB888 */
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mode_flags = 0;
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flags = V_DSP_OUT_MODE(mode_flags) |
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V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
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V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
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clrsetbits_le32(®s->dsp_ctrl0,
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M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
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flags);
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writel(V_HSYNC(hsync_len) |
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V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
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®s->dsp_htotal_hs_end);
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writel(V_HEAP(hsync_len + hback_porch + hactive) |
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V_HASP(hsync_len + hback_porch),
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®s->dsp_hact_st_end);
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writel(V_VSYNC(vsync_len) |
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V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
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®s->dsp_vtotal_vs_end);
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writel(V_VAEP(vsync_len + vback_porch + vactive)|
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V_VASP(vsync_len + vback_porch),
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®s->dsp_vact_st_end);
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writel(V_HEAP(hsync_len + hback_porch + hactive) |
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V_HASP(hsync_len + hback_porch),
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®s->post_dsp_hact_info);
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writel(V_VAEP(vsync_len + vback_porch + vactive)|
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V_VASP(vsync_len + vback_porch),
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®s->post_dsp_vact_info);
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writel(0x01, ®s->reg_cfg_done); /* enable reg config */
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}
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/**
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* rk_display_init() - Try to enable the given display device
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*
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* This function performs many steps:
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* - Finds the display device being referenced by @ep_node
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* - Puts the VOP's ID into its uclass platform data
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* - Probes the device to set it up
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* - Reads the EDID timing information
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* - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
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* - Enables the display (the display device handles this and will do different
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* things depending on the display type)
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* - Tells the uclass about the display resolution so that the console will
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* appear correctly
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*
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* @dev: VOP device that we want to connect to the display
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* @fbbase: Frame buffer address
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* @l2bpp Log2 of bits-per-pixels for the display
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* @ep_node: Device tree node to process - this is the offset of an endpoint
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* node within the VOP's 'port' list.
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* @return 0 if OK, -ve if something went wrong
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*/
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int rk_display_init(struct udevice *dev, ulong fbbase,
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enum video_log2_bpp l2bpp, int ep_node)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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const void *blob = gd->fdt_blob;
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struct rk_vop_priv *priv = dev_get_priv(dev);
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int vop_id, remote_vop_id;
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struct rk3288_vop *regs = priv->regs;
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struct display_timing timing;
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struct udevice *disp;
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int ret, remote, i, offset;
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struct display_plat *disp_uc_plat;
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struct clk clk;
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vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
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debug("vop_id=%d\n", vop_id);
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remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
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if (remote < 0)
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return -EINVAL;
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remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
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debug("remote vop_id=%d\n", remote_vop_id);
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for (i = 0, offset = remote; i < 3 && offset > 0; i++)
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offset = fdt_parent_offset(blob, offset);
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if (offset < 0) {
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debug("%s: Invalid remote-endpoint position\n", dev->name);
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return -EINVAL;
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}
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ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
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if (ret) {
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debug("%s: device '%s' display not found (ret=%d)\n", __func__,
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dev->name, ret);
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return ret;
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}
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disp_uc_plat = dev_get_uclass_platdata(disp);
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debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
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if (display_in_use(disp)) {
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debug(" - device in use\n");
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return -EBUSY;
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}
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disp_uc_plat->source_id = remote_vop_id;
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disp_uc_plat->src_dev = dev;
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ret = device_probe(disp);
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if (ret) {
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debug("%s: device '%s' display won't probe (ret=%d)\n",
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__func__, dev->name, ret);
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return ret;
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}
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ret = display_read_timing(disp, &timing);
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if (ret) {
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debug("%s: Failed to read timings\n", __func__);
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return ret;
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}
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ret = clk_get_by_index(dev, 1, &clk);
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if (!ret)
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ret = clk_set_rate(&clk, timing.pixelclock.typ);
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if (ret) {
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debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
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return ret;
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}
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rkvop_mode_set(regs, &timing, vop_id);
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rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
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ret = display_enable(disp, 1 << l2bpp, &timing);
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if (ret)
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return ret;
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uc_priv->xsize = timing.hactive.typ;
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uc_priv->ysize = timing.vactive.typ;
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uc_priv->bpix = l2bpp;
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debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
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return 0;
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}
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static int rk_vop_probe(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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const void *blob = gd->fdt_blob;
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struct rk_vop_priv *priv = dev_get_priv(dev);
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struct udevice *reg;
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int ret, port, node;
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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priv->regs = (struct rk3288_vop *)dev_get_addr(dev);
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/* lcdc(vop) iodomain select 1.8V */
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rk_setreg(&priv->grf->io_vsel, 1 << 0);
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/*
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* Try some common regulators. We should really get these from the
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* device tree somehow.
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*/
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ret = regulator_autoset_by_name("vcc18_lcd", ®);
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if (ret)
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debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
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ret = regulator_autoset_by_name("VCC18_LCD", ®);
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if (ret)
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debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
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ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", ®);
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if (ret) {
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debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
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__func__);
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}
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ret = regulator_autoset_by_name("vdd10_lcd", ®);
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if (ret) {
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debug("%s: Cannot autoset regulator vdd10_lcd\n",
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__func__);
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}
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ret = regulator_autoset_by_name("VDD10_LCD", ®);
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if (ret) {
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debug("%s: Cannot autoset regulator VDD10_LCD\n",
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__func__);
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}
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ret = regulator_autoset_by_name("vcc33_lcd", ®);
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if (ret)
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debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);
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/*
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* Try all the ports until we find one that works. In practice this
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* tries EDP first if available, then HDMI.
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*
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* Note that rockchip_vop_set_clk() always uses NPLL as the source
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* clock so it is currently not possible to use more than one display
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* device simultaneously.
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*/
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port = fdt_subnode_offset(blob, dev->of_offset, "port");
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if (port < 0)
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return -EINVAL;
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for (node = fdt_first_subnode(blob, port);
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node > 0;
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node = fdt_next_subnode(blob, node)) {
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ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
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if (ret)
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debug("Device failed: ret=%d\n", ret);
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if (!ret)
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break;
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}
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video_set_flush_dcache(dev, 1);
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return ret;
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}
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static int rk_vop_bind(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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plat->size = 1920 * 1080 * 2;
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return 0;
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}
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static const struct video_ops rk_vop_ops = {
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};
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static const struct udevice_id rk_vop_ids[] = {
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{ .compatible = "rockchip,rk3288-vop" },
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{ }
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};
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U_BOOT_DRIVER(rk_vop) = {
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.name = "rk_vop",
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.id = UCLASS_VIDEO,
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.of_match = rk_vop_ids,
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.ops = &rk_vop_ops,
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.bind = rk_vop_bind,
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.probe = rk_vop_probe,
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.priv_auto_alloc_size = sizeof(struct rk_vop_priv),
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};
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