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https://github.com/brain-hackers/u-boot-brain
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![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
254 lines
7.0 KiB
C
254 lines
7.0 KiB
C
/*
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* Copyright 2016 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <panel.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lvds_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/video/rk3288.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct rk_lvds_priv - private rockchip lvds display driver info
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*
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* @reg: LVDS register address
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* @grf: GRF register
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* @panel: Panel device that is used in driver
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*
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* @output: Output mode, decided single or double channel,
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* LVDS or LVTLL
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* @format: Data format that RGB data will packing as
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*/
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struct rk_lvds_priv {
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void __iomem *regs;
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struct rk3288_grf *grf;
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struct udevice *panel;
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int output;
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int format;
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};
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static inline void lvds_writel(struct rk_lvds_priv *lvds, u32 offset, u32 val)
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{
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writel(val, lvds->regs + offset);
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writel(val, lvds->regs + offset + 0x100);
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}
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int rk_lvds_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct rk_lvds_priv *priv = dev_get_priv(dev);
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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int ret = 0;
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unsigned int val = 0;
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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debug("%s: backlight error: %d\n", __func__, ret);
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return ret;
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}
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/* Select the video source */
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if (uc_plat->source_id)
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val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT |
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(RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16);
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else
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val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16;
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rk_setreg(&priv->grf->soc_con6, val);
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/* Select data transfer format */
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val = priv->format;
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if (priv->output == LVDS_OUTPUT_DUAL)
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val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN;
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else if (priv->output == LVDS_OUTPUT_SINGLE)
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val |= LVDS_CH0_EN;
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else if (priv->output == LVDS_OUTPUT_RGB)
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val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN;
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val |= (0xffff << 16);
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rk_setreg(&priv->grf->soc_con7, val);
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/* Enable LVDS PHY */
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if (priv->output == LVDS_OUTPUT_RGB) {
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lvds_writel(priv, RK3288_LVDS_CH0_REG0,
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RK3288_LVDS_CH0_REG0_TTL_EN |
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RK3288_LVDS_CH0_REG0_LANECK_EN |
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RK3288_LVDS_CH0_REG0_LANE4_EN |
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RK3288_LVDS_CH0_REG0_LANE3_EN |
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RK3288_LVDS_CH0_REG0_LANE2_EN |
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RK3288_LVDS_CH0_REG0_LANE1_EN |
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RK3288_LVDS_CH0_REG0_LANE0_EN);
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lvds_writel(priv, RK3288_LVDS_CH0_REG2,
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RK3288_LVDS_PLL_FBDIV_REG2(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG3,
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RK3288_LVDS_PLL_FBDIV_REG3(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG4,
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RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE |
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RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE);
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lvds_writel(priv, RK3288_LVDS_CH0_REG5,
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RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA |
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RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA);
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lvds_writel(priv, RK3288_LVDS_CH0_REGD,
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RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
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lvds_writel(priv, RK3288_LVDS_CH0_REG20,
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RK3288_LVDS_CH0_REG20_LSB);
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} else {
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lvds_writel(priv, RK3288_LVDS_CH0_REG0,
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RK3288_LVDS_CH0_REG0_LVDS_EN |
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RK3288_LVDS_CH0_REG0_LANECK_EN |
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RK3288_LVDS_CH0_REG0_LANE4_EN |
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RK3288_LVDS_CH0_REG0_LANE3_EN |
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RK3288_LVDS_CH0_REG0_LANE2_EN |
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RK3288_LVDS_CH0_REG0_LANE1_EN |
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RK3288_LVDS_CH0_REG0_LANE0_EN);
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lvds_writel(priv, RK3288_LVDS_CH0_REG1,
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RK3288_LVDS_CH0_REG1_LANECK_BIAS |
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RK3288_LVDS_CH0_REG1_LANE4_BIAS |
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RK3288_LVDS_CH0_REG1_LANE3_BIAS |
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RK3288_LVDS_CH0_REG1_LANE2_BIAS |
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RK3288_LVDS_CH0_REG1_LANE1_BIAS |
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RK3288_LVDS_CH0_REG1_LANE0_BIAS);
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lvds_writel(priv, RK3288_LVDS_CH0_REG2,
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RK3288_LVDS_CH0_REG2_RESERVE_ON |
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RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE |
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RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE |
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RK3288_LVDS_PLL_FBDIV_REG2(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG3,
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RK3288_LVDS_PLL_FBDIV_REG3(0x46));
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lvds_writel(priv, RK3288_LVDS_CH0_REG4, 0x00);
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lvds_writel(priv, RK3288_LVDS_CH0_REG5, 0x00);
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lvds_writel(priv, RK3288_LVDS_CH0_REGD,
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RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
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lvds_writel(priv, RK3288_LVDS_CH0_REG20,
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RK3288_LVDS_CH0_REG20_LSB);
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}
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/* Power on */
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writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE,
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priv->regs + RK3288_LVDS_CFG_REGC);
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writel(RK3288_LVDS_CFG_REG21_TX_ENABLE,
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priv->regs + RK3288_LVDS_CFG_REG21);
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return 0;
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}
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int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
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{
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if (fdtdec_decode_display_timing
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(gd->fdt_blob, dev->of_offset, 0, timing)) {
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debug("%s: Failed to decode display timing\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_lvds_priv *priv = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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int node = dev->of_offset;
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int ret;
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priv->regs = (void *)dev_get_addr(dev);
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
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if (ret != -1) {
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priv->output = ret;
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debug("LVDS output : %d\n", ret);
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} else {
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/* default set it as output rgb */
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priv->output = LVDS_OUTPUT_RGB;
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}
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ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
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if (ret != -1) {
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priv->format = ret;
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debug("LVDS data-mapping : %d\n", ret);
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} else {
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/* default set it as format jeida */
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priv->format = LVDS_FORMAT_JEIDA;
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}
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ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
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if (ret != -1) {
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debug("LVDS data-width : %d\n", ret);
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if (ret == 24) {
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priv->format |= LVDS_24BIT;
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} else if (ret == 18) {
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priv->format |= LVDS_18BIT;
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} else {
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debug("rockchip-lvds unsupport data-width[%d]\n", ret);
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ret = -EINVAL;
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return ret;
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}
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} else {
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priv->format |= LVDS_24BIT;
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}
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return 0;
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}
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int rk_lvds_probe(struct udevice *dev)
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{
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struct rk_lvds_priv *priv = dev_get_priv(dev);
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int ret;
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ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
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&priv->panel);
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if (ret) {
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debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
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dev->name, ret);
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return ret;
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}
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return 0;
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}
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static const struct dm_display_ops lvds_rockchip_ops = {
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.read_timing = rk_lvds_read_timing,
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.enable = rk_lvds_enable,
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};
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static const struct udevice_id rockchip_lvds_ids[] = {
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{.compatible = "rockchip,rk3288-lvds"},
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{}
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};
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U_BOOT_DRIVER(lvds_rockchip) = {
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.name = "lvds_rockchip",
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.id = UCLASS_DISPLAY,
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.of_match = rockchip_lvds_ids,
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.ops = &lvds_rockchip_ops,
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.ofdata_to_platdata = rk_lvds_ofdata_to_platdata,
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.probe = rk_lvds_probe,
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.priv_auto_alloc_size = sizeof(struct rk_lvds_priv),
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};
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