mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-01 06:48:52 +09:00
d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
84 lines
2.0 KiB
C
84 lines
2.0 KiB
C
/*
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* Copyright 2016 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <pwm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pwm.h>
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struct tegra_pwm_priv {
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struct pwm_ctlr *regs;
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};
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static int tegra_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct tegra_pwm_priv *priv = dev_get_priv(dev);
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struct pwm_ctlr *regs = priv->regs;
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uint pulse_width;
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u32 reg;
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if (channel >= 4)
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return -EINVAL;
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debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
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/* We ignore the period here and just use 32KHz */
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clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
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pulse_width = duty_ns * 255 / period_ns;
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reg = pulse_width << PWM_WIDTH_SHIFT;
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reg |= 1 << PWM_DIVIDER_SHIFT;
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writel(reg, ®s[channel].control);
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debug("%s: pulse_width=%u\n", __func__, pulse_width);
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return 0;
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}
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static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct tegra_pwm_priv *priv = dev_get_priv(dev);
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struct pwm_ctlr *regs = priv->regs;
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if (channel >= 4)
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return -EINVAL;
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debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
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clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK,
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enable ? PWM_ENABLE_MASK : 0);
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return 0;
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}
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static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
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{
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struct tegra_pwm_priv *priv = dev_get_priv(dev);
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priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
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return 0;
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}
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static const struct pwm_ops tegra_pwm_ops = {
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.set_config = tegra_pwm_set_config,
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.set_enable = tegra_pwm_set_enable,
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};
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static const struct udevice_id tegra_pwm_ids[] = {
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{ .compatible = "nvidia,tegra124-pwm" },
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{ .compatible = "nvidia,tegra20-pwm" },
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{ }
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};
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U_BOOT_DRIVER(tegra_pwm) = {
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.name = "tegra_pwm",
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.id = UCLASS_PWM,
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.of_match = tegra_pwm_ids,
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.ops = &tegra_pwm_ops,
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.ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),
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};
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