mirror of
https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
287 lines
6.6 KiB
C
287 lines
6.6 KiB
C
/*
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* Copyright (c) 2010-2016, NVIDIA CORPORATION.
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* (based on tegra_gpio.c)
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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#include <asm/gpio.h>
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#include <dm/device-internal.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "tegra186_gpio_priv.h"
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struct tegra186_gpio_port_data {
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const char *name;
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uint32_t offset;
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};
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struct tegra186_gpio_ctlr_data {
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const struct tegra186_gpio_port_data *ports;
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uint32_t port_count;
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};
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struct tegra186_gpio_platdata {
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const char *name;
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uint32_t *regs;
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};
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static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
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uint32_t gpio)
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{
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struct tegra186_gpio_platdata *plat = dev->platdata;
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uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
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return &(plat->regs[index]);
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}
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static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
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bool output)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
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rval = readl(reg);
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if (output)
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rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
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else
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rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
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writel(rval, reg);
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
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rval = readl(reg);
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if (output)
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rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
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else
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rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
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rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
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writel(rval, reg);
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return 0;
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}
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static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
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rval = readl(reg);
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if (val)
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rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
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else
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rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
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writel(rval, reg);
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return 0;
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}
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static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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return tegra186_gpio_set_out(dev, offset, false);
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}
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static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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int ret;
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ret = tegra186_gpio_set_val(dev, offset, value != 0);
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if (ret)
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return ret;
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return tegra186_gpio_set_out(dev, offset, true);
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}
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static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
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rval = readl(reg);
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if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
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offset);
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else
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
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rval = readl(reg);
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return !!rval;
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}
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static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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return tegra186_gpio_set_val(dev, offset, value != 0);
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}
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static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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uint32_t *reg;
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uint32_t rval;
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reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
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rval = readl(reg);
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if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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int gpio, port, ret;
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gpio = args->args[0];
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port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
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ret = device_get_child(dev, port, &desc->dev);
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if (ret)
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return ret;
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desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops tegra186_gpio_ops = {
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.direction_input = tegra186_gpio_direction_input,
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.direction_output = tegra186_gpio_direction_output,
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.get_value = tegra186_gpio_get_value,
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.set_value = tegra186_gpio_set_value,
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.get_function = tegra186_gpio_get_function,
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.xlate = tegra186_gpio_xlate,
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};
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/**
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* We have a top-level GPIO device with no actual GPIOs. It has a child device
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* for each port within the controller.
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*/
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static int tegra186_gpio_bind(struct udevice *parent)
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{
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struct tegra186_gpio_platdata *parent_plat = parent->platdata;
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struct tegra186_gpio_ctlr_data *ctlr_data =
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(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
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uint32_t *regs;
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int port, ret;
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/* If this is a child device, there is nothing to do here */
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if (parent_plat)
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return 0;
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regs = (uint32_t *)devfdt_get_addr_name(parent, "gpio");
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if (regs == (uint32_t *)FDT_ADDR_T_NONE)
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return -EINVAL;
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for (port = 0; port < ctlr_data->port_count; port++) {
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struct tegra186_gpio_platdata *plat;
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struct udevice *dev;
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plat = calloc(1, sizeof(*plat));
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if (!plat)
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return -ENOMEM;
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plat->name = ctlr_data->ports[port].name;
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plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
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ret = device_bind(parent, parent->driver, plat->name, plat,
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-1, &dev);
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if (ret)
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return ret;
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dev_set_of_offset(dev, dev_of_offset(parent));
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}
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return 0;
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}
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static int tegra186_gpio_probe(struct udevice *dev)
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{
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struct tegra186_gpio_platdata *plat = dev->platdata;
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* Only child devices have ports */
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if (!plat)
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return 0;
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uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
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uc_priv->bank_name = plat->name;
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return 0;
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}
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static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
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{"A", 0x2000},
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{"B", 0x3000},
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{"C", 0x3200},
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{"D", 0x3400},
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{"E", 0x2200},
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{"F", 0x2400},
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{"G", 0x4200},
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{"H", 0x1000},
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{"I", 0x0800},
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{"J", 0x5000},
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{"K", 0x5200},
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{"L", 0x1200},
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{"M", 0x5600},
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{"N", 0x0000},
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{"O", 0x0200},
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{"P", 0x4000},
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{"Q", 0x0400},
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{"R", 0x0a00},
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{"T", 0x0600},
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{"X", 0x1400},
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{"Y", 0x1600},
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{"BB", 0x2600},
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{"CC", 0x5400},
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};
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static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
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.ports = tegra186_gpio_main_ports,
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.port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
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};
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static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
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{"S", 0x0200},
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{"U", 0x0400},
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{"V", 0x0800},
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{"W", 0x0a00},
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{"Z", 0x0e00},
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{"AA", 0x0c00},
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{"EE", 0x0600},
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{"FF", 0x0000},
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};
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static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
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.ports = tegra186_gpio_aon_ports,
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.port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
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};
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static const struct udevice_id tegra186_gpio_ids[] = {
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{
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.compatible = "nvidia,tegra186-gpio",
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.data = (ulong)&tegra186_gpio_main_data,
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},
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{
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.compatible = "nvidia,tegra186-gpio-aon",
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.data = (ulong)&tegra186_gpio_aon_data,
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},
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{ }
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};
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U_BOOT_DRIVER(tegra186_gpio) = {
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.name = "tegra186_gpio",
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.id = UCLASS_GPIO,
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.of_match = tegra186_gpio_ids,
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.bind = tegra186_gpio_bind,
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.probe = tegra186_gpio_probe,
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.ops = &tegra186_gpio_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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