mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 23:26:16 +09:00
fabb9297fa
According to the errata, some bits of an undocumented register in the DCSR must be set for every core in order to avoid a possible data or instruction corruption. This is required for the 2.0 revision of the P2041 that should be used as soon as available in our design. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
46 lines
1.0 KiB
INI
46 lines
1.0 KiB
INI
#
|
|
# Copyright 2012 Freescale Semiconductor, Inc.
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
# Refer docs/README.pblimage for more details about how-to configure
|
|
# and create PBL boot image
|
|
#
|
|
|
|
#PBI commands
|
|
#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
|
|
#Freescale's errarta sheet suggests it may be done with PBI
|
|
09000010 00000000
|
|
09000014 00000000
|
|
09000018 81d00000
|
|
09021008 0000f000
|
|
09021028 0000f000
|
|
09021048 0000f000
|
|
09021068 0000f000
|
|
09000018 00000000
|
|
#Initialize CPC1 as 1MB SRAM
|
|
09010000 00200400
|
|
09138000 00000000
|
|
091380c0 00000100
|
|
09010100 00000000
|
|
09010104 fff0000b
|
|
09010f00 08000000
|
|
09010000 80000000
|
|
#Configure LAW for CPC1
|
|
09000d00 00000000
|
|
09000d04 fff00000
|
|
09000d08 81000013
|
|
09000010 00000000
|
|
09000014 ff000000
|
|
09000018 81000000
|
|
#Initialize eSPI controller, default configuration is slow for eSPI to
|
|
#load data, this configuration comes from u-boot eSPI driver.
|
|
09110000 80000403
|
|
09110020 27170008
|
|
09110024 00100008
|
|
09110028 00100008
|
|
0911002c 00100008
|
|
#Flush PBL data
|
|
09138000 00000000
|
|
091380c0 00000000
|