Kever Yang faa75ad9e6 rockchip: rk3036: fix pll config for correct frequency ... There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>		2017-11-30 22:55:27 +01:00
..
clk_rk3036.c	rockchip: rk3036: Move rockchip_get_cru() out of the driver	2016-10-30 13:29:06 -06:00
Kconfig	Kconfig: Migrate BOARD_LATE_INIT to a select	2017-01-24 10:35:54 -05:00
Makefile	rockchip: rk3036: Move rockchip_get_cru() out of the driver	2016-10-30 13:29:06 -06:00
sdram_rk3036.c	rockchip: rk3036: fix pll config for correct frequency	2017-11-30 22:55:27 +01:00
syscon_rk3036.c	rockchip: rk3036: Add a simple syscon driver	2015-12-01 08:07:22 -07:00