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https://github.com/brain-hackers/u-boot-brain
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fa427438bd
BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file. Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
182 lines
3.6 KiB
Plaintext
182 lines
3.6 KiB
Plaintext
/*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Intel LPC Bus Device - 0:1f.0 */
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Device (LPCB)
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{
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Name(_ADR, 0x001f0000)
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OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
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Field(LPC0, AnyAcc, NoLock, Preserve) {
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Offset(0x08),
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SRID, 8,
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Offset(0x80),
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C1EN, 1,
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Offset(0x84)
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}
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#include "irqlinks.asl"
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/* Firmware Hub */
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Device (FWH)
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{
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Name(_HID, EISAID("INT0800"))
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Name(_CRS, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
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})
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}
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/* 8259 Interrupt Controller */
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Device (PIC)
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{
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Name(_HID, EISAID("PNP0000"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x20, 0x20, 0x01, 0x02)
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IO(Decode16, 0x24, 0x24, 0x01, 0x02)
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IO(Decode16, 0x28, 0x28, 0x01, 0x02)
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IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
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IO(Decode16, 0x30, 0x30, 0x01, 0x02)
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IO(Decode16, 0x34, 0x34, 0x01, 0x02)
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IO(Decode16, 0x38, 0x38, 0x01, 0x02)
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IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
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IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
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IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
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IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
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IO(Decode16, 0xac, 0xac, 0x01, 0x02)
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IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
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IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
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IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
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IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
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IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
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IRQNoFlags () { 2 }
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})
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}
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/* 8254 timer */
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Device (TIMR)
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{
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Name(_HID, EISAID("PNP0100"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x40, 0x40, 0x01, 0x04)
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IO(Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags() { 0 }
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})
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}
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/* HPET */
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Device (HPET)
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{
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Name(_HID, EISAID("PNP0103"))
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Name(_CID, 0x010CD041)
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Name(_CRS, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
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})
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* Internal UART */
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Device (IURT)
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{
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Name(_HID, EISAID("PNP0501"))
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Name(_UID, 1)
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Method(_STA, 0, Serialized)
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{
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/*
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* TODO:
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*
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* Need to hide the internal UART depending on whether
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* internal UART is enabled or not so that external
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* SuperIO UART can be exposed to system.
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*/
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Store(1, UI3E)
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Store(1, UI4E)
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Store(1, C1EN)
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Return (STA_VISIBLE)
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}
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Method(_DIS, 0, Serialized)
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{
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Store(0, UI3E)
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Store(0, UI4E)
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Store(0, C1EN)
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}
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Method(_CRS, 0, Serialized)
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{
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Name(BUF0, ResourceTemplate()
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{
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IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
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IRQNoFlags() { 3 }
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})
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Name(BUF1, ResourceTemplate()
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{
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IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
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IRQNoFlags() { 4 }
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})
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If (LLessEqual(SRID, 0x04)) {
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Return (BUF0)
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} Else {
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Return (BUF1)
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}
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}
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}
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/* Real Time Clock */
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Device (RTC)
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{
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Name(_HID, EISAID("PNP0B00"))
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Name(_CRS, ResourceTemplate()
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{
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IO(Decode16, 0x70, 0x70, 1, 8)
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/*
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* Disable as Windows doesn't like it, and systems
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* don't seem to use it
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*/
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/* IRQNoFlags() { 8 } */
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})
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}
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/* LPC device: Resource consumption */
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Device (LDRC)
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{
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Name(_HID, EISAID("PNP0C02"))
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Name(_UID, 2)
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Name(RBUF, ResourceTemplate()
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{
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IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
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IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
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IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
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IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
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})
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Method(_CRS, 0, NotSerialized)
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{
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Return (RBUF)
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}
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}
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}
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