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LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
71 lines
2.5 KiB
Plaintext
71 lines
2.5 KiB
Plaintext
Overview
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--------
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The LS1046A Development System (QDS) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The LS1046AQDS provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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LS1046AQDS board Overview
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-----------------------
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- SERDES Connections, 8 lanes supporting:
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- PCI Express - 3.0
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- SGMII, SGMII 2.5
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- QSGMII
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- SATA 3.0
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- XFI
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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-IFC/Local Bus
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- One in-socket 128 MB NOR flash 16-bit data bus
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- One 512 MB NAND flash with ECC support
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- PromJet Port
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- FPGA connection
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- USB 3.0
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- Three high speed USB 3.0 ports
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- First USB 3.0 port configured as Host with Type-A connector
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- The other two USB 3.0 ports configured as OTG with micro-AB connector
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- SDHC port connects directly to an adapter card slot, featuring:
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- Optional clock feedback paths, and optional high-speed voltage translation assistance
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- SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
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- eMMC memory devices
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- DSPI: Onboard support for three SPI flash memory devices
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- 4 I2C controllers
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- One SATA onboard connectors
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
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0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB
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0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB
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0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
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0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
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0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
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0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
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0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
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0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
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0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
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Booting Options
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---------------
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a) Promjet Boot
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b) NOR boot
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c) NAND boot
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d) SD boot
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e) QSPI boot
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