mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 14:46:21 +09:00
a62c60610f
This commit adds support for the Toradex Colibri iMX7D 1GB Computer on Module. The module is very similar to the Colibri iMX7D 512MB but uses eMMC instead of raw NAND. This patch introduces a new board specific Kconfig symbol to select between the two flash options. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
476 lines
13 KiB
C
476 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016-2018 Toradex AG
|
|
*/
|
|
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/mx7-pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/gpio.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/io.h>
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <dm/platform_data/serial_mxc.h>
|
|
#include <fdt_support.h>
|
|
#include <fsl_esdhc.h>
|
|
#include <jffs2/load_kernel.h>
|
|
#include <linux/sizes.h>
|
|
#include <mmc.h>
|
|
#include <miiphy.h>
|
|
#include <mtd_node.h>
|
|
#include <netdev.h>
|
|
#include <power/pmic.h>
|
|
#include <power/rn5t567_pmic.h>
|
|
#include <usb.h>
|
|
#include <usb/ehci-ci.h>
|
|
#include "../common/tdx-common.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
|
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
|
|
|
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
|
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
|
|
|
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
|
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
|
|
|
|
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
|
|
|
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
|
|
PAD_CTL_DSE_3P3V_49OHM)
|
|
|
|
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
|
|
|
|
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
|
|
|
|
#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
|
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
|
MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
|
|
MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX7
|
|
static iomux_v3_cfg_t const usb_cdet_pads[] = {
|
|
MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
|
|
static iomux_v3_cfg_t const gpmi_pads[] = {
|
|
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
|
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
|
|
};
|
|
|
|
static void setup_gpmi_nand(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
|
|
|
|
/* NAND_USDHC_BUS_CLK is set in rom */
|
|
set_clk_nand();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
|
|
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
|
|
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
|
|
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_VIDEO_MXS
|
|
static iomux_v3_cfg_t const lcd_pads[] = {
|
|
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const backlight_pads[] = {
|
|
/* Backlight On */
|
|
MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
/* Backlight PWM<A> (multiplexed pin) */
|
|
MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
|
|
#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
|
|
|
|
static int setup_lcd(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
|
|
|
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
|
|
|
|
/* Set BL_ON */
|
|
gpio_request(GPIO_BL_ON, "BL_ON");
|
|
gpio_direction_output(GPIO_BL_ON, 1);
|
|
|
|
/* Set PWM<A> to full brightness (assuming inversed polarity) */
|
|
gpio_request(GPIO_PWM_A, "PWM<A>");
|
|
gpio_direction_output(GPIO_PWM_A, 0);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
static iomux_v3_cfg_t const fec1_pads[] = {
|
|
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
|
|
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
|
|
#else
|
|
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
#endif
|
|
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
|
MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
|
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
|
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_iomux_fec(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
|
}
|
|
#endif
|
|
|
|
static void setup_iomux_uart(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
|
|
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
|
|
|
|
static struct fsl_esdhc_cfg usdhc_cfg[] = {
|
|
#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
|
|
{USDHC3_BASE_ADDR},
|
|
#endif
|
|
{USDHC1_BASE_ADDR, 0, 4},
|
|
};
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
int ret = 0;
|
|
|
|
switch (cfg->esdhc_base) {
|
|
case USDHC1_BASE_ADDR:
|
|
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
|
break;
|
|
#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
|
|
case USDHC3_BASE_ADDR:
|
|
ret = 1;
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
int i, ret;
|
|
/* USDHC1 is mmc0, USDHC3 is mmc1 */
|
|
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
switch (i) {
|
|
case 0:
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
|
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
|
|
gpio_direction_input(USDHC1_CD_GPIO);
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
break;
|
|
#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
|
|
case 1:
|
|
imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
|
|
ARRAY_SIZE(usdhc3_emmc_pads));
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
break;
|
|
#endif
|
|
default:
|
|
printf("Warning: you configured more USDHC controllers"
|
|
"(%d) than supported by the board\n", i + 1);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int ret;
|
|
|
|
setup_iomux_fec();
|
|
|
|
ret = fecmxc_initialize_multi(bis, 0,
|
|
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
|
if (ret)
|
|
printf("FEC1 MXC: %s:failed\n", __func__);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int setup_fec(void)
|
|
{
|
|
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
|
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
|
|
|
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
|
|
/*
|
|
* Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
|
|
* and output it on the pin
|
|
*/
|
|
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
|
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
|
|
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
|
|
#else
|
|
/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
|
|
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
|
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
|
|
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
|
|
#endif
|
|
|
|
return set_clk_enet(ENET_50MHZ);
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
setup_fec();
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
|
|
setup_gpmi_nand();
|
|
#endif
|
|
|
|
#ifdef CONFIG_VIDEO_MXS
|
|
setup_lcd();
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX7
|
|
imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
|
|
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_DM_PMIC
|
|
int power_init_board(void)
|
|
{
|
|
struct udevice *dev;
|
|
int reg, ver;
|
|
int ret;
|
|
|
|
|
|
ret = pmic_get("rn5t567", &dev);
|
|
if (ret)
|
|
return ret;
|
|
ver = pmic_reg_read(dev, RN5T567_LSIVER);
|
|
reg = pmic_reg_read(dev, RN5T567_OTPVER);
|
|
|
|
printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
|
|
|
|
/* set judge and press timer of N_OE to minimal values */
|
|
pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
|
|
|
|
/* configure sleep slot for 3.3V Ethernet */
|
|
reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
|
|
reg = (reg & 0xf0) | reg >> 4;
|
|
pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
|
|
|
|
/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
|
|
pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
|
|
|
|
/* configure sleep slot for ARM rail */
|
|
reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
|
|
reg = (reg & 0xf0) | reg >> 4;
|
|
pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
|
|
|
|
/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
|
|
pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
struct udevice *dev;
|
|
|
|
pmic_get("rn5t567", &dev);
|
|
|
|
/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
|
|
pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
|
|
pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
|
|
|
|
/*
|
|
* Re-power factor detection on PMIC side is not instant. 1ms
|
|
* proved to be enough time until reset takes effect.
|
|
*/
|
|
mdelay(1);
|
|
}
|
|
#endif
|
|
|
|
int checkboard(void)
|
|
{
|
|
printf("Model: Toradex Colibri iMX7%c\n",
|
|
is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
|
|
static const struct node_info nodes[] = {
|
|
{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
|
|
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
|
|
};
|
|
|
|
/* Update partition nodes using info from mtdparts env var */
|
|
puts(" Updating MTD partitions...\n");
|
|
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
|
|
#endif
|
|
|
|
return ft_common_board_setup(blob, bd);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX7
|
|
static iomux_v3_cfg_t const usb_otg2_pads[] = {
|
|
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
if (is_cpu_type(MXC_CPU_MX7S))
|
|
return -ENODEV;
|
|
|
|
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
|
ARRAY_SIZE(usb_otg2_pads));
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int board_usb_phy_mode(int port)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
if (gpio_get_value(USB_CDET_GPIO))
|
|
return USB_INIT_DEVICE;
|
|
else
|
|
return USB_INIT_HOST;
|
|
case 1:
|
|
default:
|
|
return USB_INIT_HOST;
|
|
}
|
|
}
|
|
#endif
|