mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
f9f016adcd
Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
33 lines
1.0 KiB
Makefile
33 lines
1.0 KiB
Makefile
#
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# Copyright (c) 2015 Google, Inc
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
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obj-y += tegra/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_MESON) += clk_meson.o
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_SOCFPGA) += altera/
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obj-$(CONFIG_CLK_AT91) += at91/
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obj-$(CONFIG_CLK_MVEBU) += mvebu/
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obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
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obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
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obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
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obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
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obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
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obj-$(CONFIG_STM32H7) += clk_stm32h7.o
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