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![Stefan Agner](/assets/img/avatar_default.png)
Implement MIGRATE_INFO_TYPE. This informs Linux that no migration for the trusted operating system is necessary: [ 0.000000] psci: Trusted OS migration not required Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
225 lines
4.9 KiB
C
225 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include <asm/arch/imx-regs.h>
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#include <linux/bitops.h>
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#include <common.h>
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#include <fsl_wdog.h>
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#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
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#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
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#define GPC_PGC_C0 0x800
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#define GPC_PGC_C1 0x840
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#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1
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#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
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/* below is for i.MX7D */
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#define SRC_GPR1_MX7D 0x074
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#define SRC_A7RCR0 0x004
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#define SRC_A7RCR1 0x008
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#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
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#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
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#define SNVS_LPCR 0x38
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#define BP_SNVS_LPCR_DP_EN 0x20
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#define BP_SNVS_LPCR_TOP 0x40
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#define CCM_CCGR_SNVS 0x4250
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#define CCM_ROOT_WDOG 0xbb80
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#define CCM_CCGR_WDOG1 0x49c0
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#define MPIDR_AFF0 GENMASK(7, 0)
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#define IMX7D_PSCI_NR_CPUS 2
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#if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
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#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
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#endif
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u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = {
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PSCI_AFFINITY_LEVEL_ON,
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PSCI_AFFINITY_LEVEL_OFF};
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static inline void psci_set_state(int cpu, u8 state)
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{
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psci_state[cpu] = state;
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dsb();
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isb();
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}
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static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
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{
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writel(enable, GPC_IPS_BASE_ADDR + offset);
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}
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__secure void imx_gpcv2_set_core_power(int cpu, bool pdn)
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{
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u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
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u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0;
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u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 :
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BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7;
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u32 val;
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imx_gpcv2_set_m_core_pgc(true, pgc);
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val = readl(GPC_IPS_BASE_ADDR + reg);
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val |= pdn_pup_req;
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writel(val, GPC_IPS_BASE_ADDR + reg);
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while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0)
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;
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imx_gpcv2_set_m_core_pgc(false, pgc);
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}
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__secure void imx_enable_cpu_ca7(int cpu, bool enable)
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{
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u32 mask, val;
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mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
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val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
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val = enable ? val | mask : val & ~mask;
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writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
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}
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__secure void psci_arch_cpu_entry(void)
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{
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u32 cpu = psci_get_cpu_id();
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
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}
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__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep,
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u32 context_id)
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{
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u32 cpu = mpidr & MPIDR_AFF0;
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if (mpidr & ~MPIDR_AFF0)
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return ARM_PSCI_RET_INVAL;
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if (cpu >= IMX7D_PSCI_NR_CPUS)
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return ARM_PSCI_RET_INVAL;
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if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
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return ARM_PSCI_RET_ALREADY_ON;
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if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
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return ARM_PSCI_RET_ON_PENDING;
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psci_save(cpu, ep, context_id);
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writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
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imx_gpcv2_set_core_power(cpu, true);
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imx_enable_cpu_ca7(cpu, true);
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return ARM_PSCI_RET_SUCCESS;
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}
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__secure s32 psci_cpu_off(void)
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{
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int cpu;
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cpu = psci_get_cpu_id();
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psci_cpu_off_common();
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psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
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imx_enable_cpu_ca7(cpu, false);
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imx_gpcv2_set_core_power(cpu, false);
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writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
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while (1)
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wfi();
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}
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__secure void psci_system_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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/* make sure WDOG1 clock is enabled */
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writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
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writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
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writew(WCR_WDE, &wdog->wcr);
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while (1)
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wfi();
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}
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__secure void psci_system_off(void)
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{
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u32 val;
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/* make sure SNVS clock is enabled */
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writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
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val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
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val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
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writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
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while (1)
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wfi();
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}
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__secure u32 psci_version(void)
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{
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return ARM_PSCI_VER_1_0;
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}
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__secure s32 psci_cpu_suspend(u32 __always_unused function_id, u32 power_state,
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u32 entry_point_address,
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u32 context_id)
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{
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return ARM_PSCI_RET_INVAL;
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}
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__secure s32 psci_affinity_info(u32 __always_unused function_id,
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u32 target_affinity,
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u32 lowest_affinity_level)
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{
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u32 cpu = target_affinity & MPIDR_AFF0;
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if (lowest_affinity_level > 0)
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return ARM_PSCI_RET_INVAL;
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if (target_affinity & ~MPIDR_AFF0)
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return ARM_PSCI_RET_INVAL;
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if (cpu >= IMX7D_PSCI_NR_CPUS)
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return ARM_PSCI_RET_INVAL;
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return psci_state[cpu];
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}
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__secure s32 psci_migrate_info_type(u32 function_id)
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{
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/* Trusted OS is either not present or does not require migration */
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return 2;
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}
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__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
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{
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switch (psci_fid) {
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case ARM_PSCI_0_2_FN_PSCI_VERSION:
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case ARM_PSCI_0_2_FN_CPU_OFF:
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case ARM_PSCI_0_2_FN_CPU_ON:
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case ARM_PSCI_0_2_FN_AFFINITY_INFO:
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case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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case ARM_PSCI_0_2_FN_SYSTEM_OFF:
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case ARM_PSCI_0_2_FN_SYSTEM_RESET:
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case ARM_PSCI_1_0_FN_PSCI_FEATURES:
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return 0x0;
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}
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return ARM_PSCI_RET_NI;
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}
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