39 lines
2.0 KiB
C
39 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
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*/
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#ifndef K210_SYSCTL_H
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#define K210_SYSCTL_H
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/* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */
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#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */
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#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */
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#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
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#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
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#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
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#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */
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#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */
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#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
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#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
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#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
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#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */
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#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */
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#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */
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#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */
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#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */
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#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */
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#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */
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#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */
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#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */
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#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */
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#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */
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#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */
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#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */
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#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */
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#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */
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#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */
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#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */
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#endif /* K210_SYSCTL_H */
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