615 lines
11 KiB
C
615 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_MIO_EMM_DEFS_H__
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#define __CVMX_MIO_EMM_DEFS_H__
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static inline u64 MIO_EMM_DMA_FIFO_CFG(void)
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{
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return 0x160;
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}
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static inline u64 MIO_EMM_DMA_FIFO_ADR(void)
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{
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return 0x170;
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}
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static inline u64 MIO_EMM_DMA_FIFO_CMD(void)
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{
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return 0x178;
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}
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static inline u64 MIO_EMM_DMA_CFG(void)
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{
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return 0x180;
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}
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static inline u64 MIO_EMM_DMA_ADR(void)
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{
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return 0x188;
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}
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static inline u64 MIO_EMM_DMA_INT(void)
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{
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return 0x190;
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}
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static inline u64 MIO_EMM_CFG(void)
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{
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return 0x2000;
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}
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static inline u64 MIO_EMM_MODEX(u64 a)
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{
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return 0x2008 + 8 * a;
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}
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static inline u64 MIO_EMM_SWITCH(void)
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{
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return 0x2048;
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}
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static inline u64 MIO_EMM_DMA(void)
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{
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return 0x2050;
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}
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static inline u64 MIO_EMM_CMD(void)
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{
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return 0x2058;
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}
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static inline u64 MIO_EMM_RSP_STS(void)
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{
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return 0x2060;
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}
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static inline u64 MIO_EMM_RSP_LO(void)
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{
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return 0x2068;
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}
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static inline u64 MIO_EMM_RSP_HI(void)
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{
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return 0x2070;
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}
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static inline u64 MIO_EMM_INT(void)
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{
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return 0x2078;
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}
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static inline u64 MIO_EMM_WDOG(void)
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{
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return 0x2088;
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}
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static inline u64 MIO_EMM_SAMPLE(void)
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{
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return 0x2090;
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}
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static inline u64 MIO_EMM_STS_MASK(void)
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{
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return 0x2098;
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}
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static inline u64 MIO_EMM_RCA(void)
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{
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return 0x20a0;
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}
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static inline u64 MIO_EMM_BUF_IDX(void)
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{
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return 0x20e0;
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}
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static inline u64 MIO_EMM_BUF_DAT(void)
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{
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return 0x20e8;
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}
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/* Dummy implementation, not documented on MIPS Octeon */
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static inline u64 MIO_EMM_DEBUG(void)
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{
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return 0x20f8;
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}
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/**
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* mio_emm_access_wdog
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*/
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union mio_emm_access_wdog {
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u64 u;
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struct mio_emm_access_wdog_s {
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uint64_t reserved_32_63 : 32;
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uint64_t clk_cnt : 32;
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} s;
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};
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/**
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* mio_emm_buf_dat
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*
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* MIO_EMM_BUF_DAT = MIO EMMC Data buffer access Register
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*
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*/
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union mio_emm_buf_dat {
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u64 u;
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struct mio_emm_buf_dat_s {
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uint64_t dat : 64;
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} s;
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};
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/**
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* mio_emm_buf_idx
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*
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* MIO_EMM_BUF_IDX = MIO EMMC Data buffer address Register
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*
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*/
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union mio_emm_buf_idx {
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u64 u;
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struct mio_emm_buf_idx_s {
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uint64_t reserved_17_63 : 47;
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uint64_t inc : 1;
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uint64_t reserved_7_15 : 9;
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uint64_t buf_num : 1;
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uint64_t offset : 6;
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} s;
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};
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/**
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* mio_emm_cfg
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*
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* MIO_EMM_CFG = MIO EMMC Configuration Register
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*
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*/
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union mio_emm_cfg {
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u64 u;
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struct mio_emm_cfg_s {
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uint64_t reserved_17_63 : 47;
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uint64_t boot_fail : 1;
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uint64_t reserved_4_15 : 12;
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uint64_t bus_ena : 4;
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} s;
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};
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/**
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* mio_emm_cmd
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*
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* MIO_EMM_CMD = MIO EMMC Command Register
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*
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*/
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union mio_emm_cmd {
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u64 u;
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struct mio_emm_cmd_s {
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uint64_t reserved_63_63 : 1;
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uint64_t skip_busy : 1;
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uint64_t bus_id : 2;
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uint64_t cmd_val : 1;
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uint64_t reserved_56_58 : 3;
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uint64_t dbuf : 1;
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uint64_t offset : 6;
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uint64_t reserved_43_48 : 6;
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uint64_t ctype_xor : 2;
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uint64_t rtype_xor : 3;
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uint64_t cmd_idx : 6;
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uint64_t arg : 32;
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} s;
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};
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/**
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* mio_emm_dma
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*
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* MIO_EMM_DMA = MIO EMMC DMA config Register
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*
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*/
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union mio_emm_dma {
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u64 u;
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struct mio_emm_dma_s {
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uint64_t reserved_63_63 : 1;
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uint64_t skip_busy : 1;
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uint64_t bus_id : 2;
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uint64_t dma_val : 1;
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uint64_t sector : 1;
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uint64_t dat_null : 1;
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uint64_t thres : 6;
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uint64_t rel_wr : 1;
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uint64_t rw : 1;
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uint64_t multi : 1;
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uint64_t block_cnt : 16;
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uint64_t card_addr : 32;
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} s;
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};
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/**
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* mio_emm_dma_adr
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*
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* This register sets the address for eMMC/SD flash transfers to/from memory. Sixty-four-bit
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* operations must be used to access this register. This register is updated by the DMA
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* hardware and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR.
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*/
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union mio_emm_dma_adr {
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u64 u;
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struct mio_emm_dma_adr_s {
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uint64_t reserved_42_63 : 22;
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uint64_t adr : 42;
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} s;
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};
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/**
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* mio_emm_dma_cfg
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*
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* This register controls the internal DMA engine used with the eMMC/SD flash controller. Sixty-
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* four-bit operations must be used to access this register. This register is updated by the
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* hardware DMA engine and can also be reloaded by writes to the MIO_EMM_DMA_FIFO_CMD register.
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*/
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union mio_emm_dma_cfg {
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u64 u;
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struct mio_emm_dma_cfg_s {
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uint64_t en : 1;
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uint64_t rw : 1;
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uint64_t clr : 1;
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uint64_t reserved_60_60 : 1;
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uint64_t swap32 : 1;
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uint64_t swap16 : 1;
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uint64_t swap8 : 1;
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uint64_t endian : 1;
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uint64_t size : 20;
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uint64_t reserved_0_35 : 36;
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} s;
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};
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/**
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* mio_emm_dma_fifo_adr
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*
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* This register specifies the internal address that is loaded into the eMMC internal DMA FIFO.
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* The FIFO is used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA
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* completes successfully.
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*/
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union mio_emm_dma_fifo_adr {
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u64 u;
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struct mio_emm_dma_fifo_adr_s {
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uint64_t reserved_42_63 : 22;
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uint64_t adr : 39;
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uint64_t reserved_0_2 : 3;
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} s;
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};
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/**
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* mio_emm_dma_fifo_cfg
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*
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* This register controls DMA FIFO operations.
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*
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*/
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union mio_emm_dma_fifo_cfg {
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u64 u;
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struct mio_emm_dma_fifo_cfg_s {
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uint64_t reserved_17_63 : 47;
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uint64_t clr : 1;
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uint64_t reserved_13_15 : 3;
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uint64_t int_lvl : 5;
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uint64_t reserved_5_7 : 3;
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uint64_t count : 5;
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} s;
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};
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/**
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* mio_emm_dma_fifo_cmd
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*
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* This register specifies a command that is loaded into the eMMC internal DMA FIFO. The FIFO is
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* used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes
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* successfully. Writes to this register store both the MIO_EMM_DMA_FIFO_CMD and the
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* MIO_EMM_DMA_FIFO_ADR contents into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT]
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* field.
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*
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* Note: This register has a similar format to MIO_EMM_DMA_CFG with the exception
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* that the EN and CLR fields are absent. These are supported in MIO_EMM_DMA_FIFO_CFG.
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*/
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union mio_emm_dma_fifo_cmd {
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u64 u;
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struct mio_emm_dma_fifo_cmd_s {
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uint64_t reserved_63_63 : 1;
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uint64_t rw : 1;
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uint64_t reserved_61_61 : 1;
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uint64_t intdis : 1;
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uint64_t swap32 : 1;
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uint64_t swap16 : 1;
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uint64_t swap8 : 1;
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uint64_t endian : 1;
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uint64_t size : 20;
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uint64_t reserved_0_35 : 36;
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} s;
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};
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/**
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* mio_emm_dma_int
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*
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* Sixty-four-bit operations must be used to access this register.
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*
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*/
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union mio_emm_dma_int {
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u64 u;
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struct mio_emm_dma_int_s {
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uint64_t reserved_2_63 : 62;
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uint64_t fifo : 1;
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uint64_t done : 1;
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} s;
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};
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/**
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* mio_emm_dma_int_w1s
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*/
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union mio_emm_dma_int_w1s {
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u64 u;
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struct mio_emm_dma_int_w1s_s {
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uint64_t reserved_2_63 : 62;
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uint64_t fifo : 1;
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uint64_t done : 1;
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} s;
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};
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/**
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* mio_emm_int
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*
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* MIO_EMM_INT = MIO EMMC Interrupt Register
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*
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*/
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union mio_emm_int {
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u64 u;
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struct mio_emm_int_s {
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uint64_t reserved_7_63 : 57;
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uint64_t switch_err : 1;
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uint64_t switch_done : 1;
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uint64_t dma_err : 1;
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uint64_t cmd_err : 1;
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uint64_t dma_done : 1;
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uint64_t cmd_done : 1;
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uint64_t buf_done : 1;
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} s;
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};
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/**
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* mio_emm_int_en
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*
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* MIO_EMM_INT_EN = MIO EMMC Interrupt enable Register
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*
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*/
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union mio_emm_int_en {
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u64 u;
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struct mio_emm_int_en_s {
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uint64_t reserved_7_63 : 57;
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uint64_t switch_err : 1;
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uint64_t switch_done : 1;
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uint64_t dma_err : 1;
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uint64_t cmd_err : 1;
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uint64_t dma_done : 1;
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uint64_t cmd_done : 1;
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uint64_t buf_done : 1;
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} s;
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};
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/**
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* mio_emm_int_w1s
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*/
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union mio_emm_int_w1s {
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u64 u;
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struct mio_emm_int_w1s_s {
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uint64_t reserved_7_63 : 57;
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uint64_t switch_err : 1;
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uint64_t switch_done : 1;
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uint64_t dma_err : 1;
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uint64_t cmd_err : 1;
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uint64_t dma_done : 1;
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uint64_t cmd_done : 1;
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uint64_t buf_done : 1;
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} s;
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};
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/**
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* mio_emm_mode#
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*
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* MIO_EMM_MODE = MIO EMMC Operating mode Register
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*
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*/
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union mio_emm_modex {
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u64 u;
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struct mio_emm_modex_s {
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uint64_t reserved_49_63 : 15;
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uint64_t hs_timing : 1;
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uint64_t reserved_43_47 : 5;
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uint64_t bus_width : 3;
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uint64_t reserved_36_39 : 4;
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uint64_t power_class : 4;
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uint64_t clk_hi : 16;
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uint64_t clk_lo : 16;
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} s;
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};
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/**
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* mio_emm_rca
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*/
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union mio_emm_rca {
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u64 u;
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struct mio_emm_rca_s {
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uint64_t reserved_16_63 : 48;
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uint64_t card_rca : 16;
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} s;
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};
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/**
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* mio_emm_rsp_hi
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*
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* MIO_EMM_RSP_HI = MIO EMMC Response data high Register
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*
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*/
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union mio_emm_rsp_hi {
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u64 u;
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struct mio_emm_rsp_hi_s {
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uint64_t dat : 64;
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} s;
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};
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/**
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* mio_emm_rsp_lo
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*
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* MIO_EMM_RSP_LO = MIO EMMC Response data low Register
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*
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*/
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union mio_emm_rsp_lo {
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u64 u;
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struct mio_emm_rsp_lo_s {
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uint64_t dat : 64;
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} s;
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};
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/**
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* mio_emm_rsp_sts
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*
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* MIO_EMM_RSP_STS = MIO EMMC Response status Register
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*
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*/
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union mio_emm_rsp_sts {
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u64 u;
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struct mio_emm_rsp_sts_s {
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uint64_t reserved_62_63 : 2;
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uint64_t bus_id : 2;
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uint64_t cmd_val : 1;
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uint64_t switch_val : 1;
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uint64_t dma_val : 1;
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uint64_t dma_pend : 1;
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uint64_t acc_timeout : 1;
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uint64_t reserved_29_54 : 26;
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uint64_t dbuf_err : 1;
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uint64_t reserved_24_27 : 4;
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uint64_t dbuf : 1;
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uint64_t blk_timeout : 1;
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uint64_t blk_crc_err : 1;
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uint64_t rsp_busybit : 1;
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uint64_t stp_timeout : 1;
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uint64_t stp_crc_err : 1;
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uint64_t stp_bad_sts : 1;
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uint64_t stp_val : 1;
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uint64_t rsp_timeout : 1;
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uint64_t rsp_crc_err : 1;
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uint64_t rsp_bad_sts : 1;
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uint64_t rsp_val : 1;
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uint64_t rsp_type : 3;
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uint64_t cmd_type : 2;
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uint64_t cmd_idx : 6;
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uint64_t cmd_done : 1;
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} s;
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};
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/**
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* mio_emm_sample
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*/
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union mio_emm_sample {
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u64 u;
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struct mio_emm_sample_s {
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uint64_t reserved_26_63 : 38;
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uint64_t cmd_cnt : 10;
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uint64_t reserved_10_15 : 6;
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uint64_t dat_cnt : 10;
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} s;
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};
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/**
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* mio_emm_sts_mask
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*/
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union mio_emm_sts_mask {
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u64 u;
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struct mio_emm_sts_mask_s {
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uint64_t reserved_32_63 : 32;
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uint64_t sts_msk : 32;
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} s;
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};
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/**
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* mio_emm_switch
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*
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* MIO_EMM_SWITCH = MIO EMMC Operating mode switch Register
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*
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*/
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union mio_emm_switch {
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u64 u;
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struct mio_emm_switch_s {
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uint64_t reserved_62_63 : 2;
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uint64_t bus_id : 2;
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uint64_t switch_exe : 1;
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uint64_t switch_err0 : 1;
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uint64_t switch_err1 : 1;
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uint64_t switch_err2 : 1;
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uint64_t reserved_49_55 : 7;
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uint64_t hs_timing : 1;
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uint64_t reserved_43_47 : 5;
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uint64_t bus_width : 3;
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uint64_t reserved_36_39 : 4;
|
|
uint64_t power_class : 4;
|
|
uint64_t clk_hi : 16;
|
|
uint64_t clk_lo : 16;
|
|
} s;
|
|
};
|
|
|
|
/**
|
|
* mio_emm_wdog
|
|
*
|
|
* MIO_EMM_WDOG = MIO EMMC Watchdog Register
|
|
*
|
|
*/
|
|
union mio_emm_wdog {
|
|
u64 u;
|
|
struct mio_emm_wdog_s {
|
|
uint64_t reserved_26_63 : 38;
|
|
uint64_t clk_cnt : 26;
|
|
} s;
|
|
};
|
|
|
|
/*
|
|
* The following structs are only available to enable compilation of the common
|
|
* MMC driver. These registers do not exist on MIPS Octeon.
|
|
*/
|
|
|
|
/**
|
|
* Register (RSL) mio_emm_timing
|
|
*
|
|
* eMMC Timing Register This register determines the number of tap delays
|
|
* the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in
|
|
* relation to EMM_CLK. These values should only be changed when the eMMC
|
|
* bus is idle.
|
|
*/
|
|
union mio_emm_timing {
|
|
u64 u;
|
|
struct mio_emm_timing_s {
|
|
u64 data_out_tap : 6;
|
|
u64 reserved_6_15 : 10;
|
|
u64 data_in_tap : 6;
|
|
u64 reserved_22_31 : 10;
|
|
u64 cmd_out_tap : 6;
|
|
u64 reserved_38_47 : 10;
|
|
u64 cmd_in_tap : 6;
|
|
u64 reserved_54_63 : 10;
|
|
} s;
|
|
};
|
|
|
|
/**
|
|
* Register (RSL) mio_emm_debug
|
|
*
|
|
* eMMC Debug Register
|
|
*/
|
|
union mio_emm_debug {
|
|
u64 u;
|
|
struct mio_emm_debug_s {
|
|
u64 clk_on : 1;
|
|
u64 reserved_1_7 : 7;
|
|
u64 cmd_sm : 4;
|
|
u64 data_sm : 4;
|
|
u64 dma_sm : 4;
|
|
u64 emmc_clk_disable : 1;
|
|
u64 rdsync_rst : 1;
|
|
u64 reserved_22_63 : 42;
|
|
} s;
|
|
};
|
|
|
|
#endif
|