mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
f9917454d5
It is common for system reset to be available at multiple levels in modern hardware. For example, an SoC may provide a reset option, and a board may provide its own reset for reasons of security or thoroughness. It is useful to be able to model this hardware without hard-coding the behaviour in the SoC or board. Also there is a distinction sometimes between resetting just the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting power. To achieve this, add a simple system reset uclass. It allows multiple devices to provide reset functionality and provides a way to walk through them, requesting a particular reset type until is it provided. Signed-off-by: Simon Glass <sjg@chromium.org>
85 lines
2.9 KiB
Plaintext
85 lines
2.9 KiB
Plaintext
config CMD_CROS_EC
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bool "Enable crosec command"
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depends on CROS_EC
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help
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Enable command-line access to the Chrome OS EC (Embedded
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Controller). This provides the 'crosec' command which has
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a number of sub-commands for performing EC tasks such as
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updating its flash, accessing a small saved context area
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and talking to the I2C bus behind the EC (if there is one).
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config CROS_EC
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bool "Enable Chrome OS EC"
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help
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Enable access to the Chrome OS EC. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config CROS_EC_I2C
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bool "Enable Chrome OS EC I2C driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on older
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ARM Chromebooks such as snow and spring before the standard bus
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changed to SPI. The EC will accept commands across the I2C using
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a special message protocol, and provide responses.
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config CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver"
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depends on CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config CROS_EC_SPI
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bool "Enable Chrome OS EC SPI driver"
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depends on CROS_EC
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help
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Enable SPI access to the Chrome OS EC. This is used on newer
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ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
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provides a faster and more robust interface than I2C but the bugs
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are less interesting.
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config CONFIG_FSL_SEC_MON
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bool "Enable FSL SEC_MON Driver"
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help
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Freescale Security Monitor block is responsible for monitoring
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system states.
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Security Monitor can be transitioned on any security failures,
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like software violations or hardware security violations.
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config PCA9551_LED
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bool "Enable PCA9551 LED driver"
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help
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Enable driver for PCA9551 LED controller. This controller
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is connected via I2C. So I2C needs to be enabled.
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config PCA9551_I2C_ADDR
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hex "I2C address of PCA9551 LED controller"
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depends on PCA9551_LED
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default 0x60
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help
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The I2C address of the PCA9551 LED controller.
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config RESET
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bool "Enable support for reset drivers"
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depends on DM
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help
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Enable reset drivers which can be used to reset the CPU or board.
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Each driver can provide a reset method which will be called to
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effect a reset. The uclass will try all available drivers when
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reset_walk() is called.
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