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https://github.com/brain-hackers/u-boot-brain
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59fbd5c1f8
This patch add ethernet node gem1 to zcu1275 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
109 lines
2.5 KiB
Plaintext
109 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP ZCU1275 RevB
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*
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* (C) Copyright 2018 - 2020, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP ZCU1275 RevB";
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compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
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"xlnx,zynqmp";
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aliases {
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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mmc0 = &sdhci1;
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ethernet0 = &gem1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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&dcc {
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status = "okay";
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};
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&gem1 {
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
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rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
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txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
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txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
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rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
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rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
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rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
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rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
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rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
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txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
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txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
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txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
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txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
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};
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};
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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partition@0 { /* for testing purpose */
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@100000 { /* for testing purpose */
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@600000 { /* for testing purpose */
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@620000 { /* for testing purpose */
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&sdhci1 {
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status = "okay";
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/*
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* 1.0 revision has level shifter and this property should be
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* removed for supporting UHS mode
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*/
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no-1-8-v;
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xlnx,mio-bank = <1>;
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};
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