mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
8e95883e46
Beacon EmbeddedWorks is releasing a devkit based on the i.MX8M Nano SoC consisting of baseboard + SOM. The kit is based on the same design as the Beacon dev kit with the i.MX8M Mini. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
237 lines
5.1 KiB
Plaintext
237 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2020 Compass Electronics Group, LLC
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*/
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/ {
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leds {
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compatible = "gpio-leds";
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led-0 {
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label = "gen_led0";
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gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-1 {
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label = "gen_led1";
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gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-2 {
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label = "gen_led2";
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gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led3>;
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label = "heartbeat";
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gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "vsd_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg_vbus: regulator-usb {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb_otg>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_espi2>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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eeprom@0 {
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compatible = "microchip,at25160bn", "atmel,at25";
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reg = <0>;
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spi-max-frequency = <5000000>;
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spi-cpha;
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spi-cpol;
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pagesize = <32>;
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size = <2048>;
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address-width = <16>;
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};
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};
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&i2c4 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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pca6416_0: gpio@20 {
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compatible = "nxp,pcal6416";
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reg = <0x20>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcal6414>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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};
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pca6416_1: gpio@21 {
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compatible = "nxp,pcal6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart2 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MN_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg_vbus>;
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disable-over-current;
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dr_mode="otg";
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_espi2: espi2grp {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
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MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
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MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
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MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
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MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
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>;
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};
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pinctrl_led3: led3grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
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>;
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};
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pinctrl_pcal6414: pcal6414-gpiogrp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
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>;
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};
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pinctrl_reg_usb_otg: reg-otggrp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
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MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
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MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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};
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