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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
161 lines
3.4 KiB
C
161 lines
3.4 KiB
C
/*
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* (c) 2010 Graf-Syteco, Matthias Weisser
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* <weisserm@arcor.de>
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*
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* (C) Copyright 2007, mycable GmbH
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* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mb86r0x.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
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MB86R0x_CCNT_BASE;
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/* We select mode 0 for group 2 and mode 1 for group 4 */
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writel(0x00000010, &ccnt->cmux_md);
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gd->flags = 0;
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gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
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icache_enable();
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dcache_enable();
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return 0;
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}
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static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
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unsigned long pwm_base)
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{
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struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
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MB86R0x_GPIO_BASE;
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struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
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const char *e;
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writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
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e = getenv(pwm_opts);
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if (e != NULL) {
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const char *s;
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uint32_t freq, init;
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freq = 0;
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init = 0;
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s = strchr(e, 'f');
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if (s != NULL)
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freq = simple_strtol(s + 2, NULL, 0);
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s = strchr(e, 'i');
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if (s != NULL)
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init = simple_strtol(s + 2, NULL, 0);
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if (freq > 0) {
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writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
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&pwm->bcr);
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writel(1002, &pwm->tpr);
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writel(1, &pwm->pr);
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writel(init * 10 + 1, &pwm->dr);
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writel(1, &pwm->cr);
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writel(1, &pwm->sr);
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}
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}
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}
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int board_late_init(void)
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{
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struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
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MB86R0x_GPIO_BASE;
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uint32_t in_word;
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#ifdef CONFIG_VIDEO_MB86R0xGDC
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/* Check if we have valid display settings and turn on power if so */
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/* Display 0 */
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if (getenv("gs_dsp_0_param") || getenv("videomode"))
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setup_display_power((1 << 3), "gs_dsp_0_pwm",
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MB86R0x_PWM0_BASE);
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/* The corresponding GPIO is always an output */
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writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
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/* Display 1 */
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if (getenv("gs_dsp_1_param") || getenv("videomode1"))
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setup_display_power((1 << 4), "gs_dsp_1_pwm",
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MB86R0x_PWM1_BASE);
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/* The corresponding GPIO is always an output */
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writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
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#endif /* CONFIG_VIDEO_MB86R0xGDC */
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/* 5V enable */
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writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
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writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
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/* We have special boot options if told by GPIOs */
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in_word = readl(&gpio->gpdr1);
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if ((in_word & 0xC0) == 0xC0) {
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setenv("stdin", "serial");
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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setenv("preboot", "run gs_slow_boot");
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} else if ((in_word & 0xC0) != 0) {
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setenv("stdout", "vga");
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setenv("preboot", "run gs_slow_boot");
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} else {
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setenv("stdin", "serial");
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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if (getenv("gs_devel")) {
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setenv("preboot", "run gs_slow_boot");
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} else {
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setenv("preboot", "run gs_fast_boot");
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}
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}
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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/*
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* DRAM configuration
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*/
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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