mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-18 18:53:22 +09:00
47f58a7357
The omap2420-h4 board is using a RAM based address as the linker location for code. This is causing several problems when attempting to run the latest u-boot code base on this board from flash. Update the default linker location for code to be in NOR flash. Please note that OMAP maps the NOR flash to address 0x08000000 by default and so use this as the default address for the NOR flash. Also remove legacy code that attempts to calculate where in flash the sdata structure, that holds the memory interface configuration data, is located. By changing the default linker location for code to flash this is no longer necessary. Signed-off-by: Jon Hunter <jon-hunter@ti.com>
237 lines
8.6 KiB
C
237 lines
8.6 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP2420_SYS_H_
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#define _OMAP2420_SYS_H_
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#include <asm/sizes.h>
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/*
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* 2420 specific Section
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*/
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/* L3 Firewall */
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#define A_REQINFOPERM0 0x68005048
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#define A_READPERM0 0x68005050
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#define A_WRITEPERM0 0x68005058
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/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */
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/* L3 Firewall */
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#define A_REQINFOPERM0 0x68005048
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#define A_READPERM0 0x68005050
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#define A_WRITEPERM0 0x68005058
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/* CONTROL */
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#define OMAP2420_CTRL_BASE (0x48000000)
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#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
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/* device type */
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* TAP information */
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#define OMAP2420_TAP_BASE (0x48014000)
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#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
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#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208)
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/* GPMC */
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#define OMAP2420_GPMC_BASE (0x6800A000)
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#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)
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#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)
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#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)
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#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)
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#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)
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#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)
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#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
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#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
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#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
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#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
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#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
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#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
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#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
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#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)
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#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)
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#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
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#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
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#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
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#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0)
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#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4)
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#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8)
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#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC)
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#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0)
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#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4)
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#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8)
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#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0)
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#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4)
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#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8)
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#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC)
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#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100)
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#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104)
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#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108)
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/* SMS */
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#define OMAP2420_SMS_BASE 0x68008000
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#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
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#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0)
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# define BURSTCOMPLETE_GROUP7 BIT31
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/* SDRC */
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#define OMAP2420_SDRC_BASE 0x68009000
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#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
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#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
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#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40)
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#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
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#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
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#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
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#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)
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#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)
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#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)
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#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
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#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
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#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
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#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
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#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)
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#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)
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#define OMAP2420_SDRC_CS0 0x80000000
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#define OMAP2420_SDRC_CS1 0xA0000000
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#define CMD_NOP 0x0
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#define CMD_PRECHARGE 0x1
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#define CMD_AUTOREFRESH 0x2
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#define CMD_ENTR_PWRDOWN 0x3
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#define CMD_EXIT_PWRDOWN 0x4
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#define CMD_ENTR_SRFRSH 0x5
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#define CMD_CKE_HIGH 0x6
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#define CMD_CKE_LOW 0x7
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#define SOFTRESET BIT1
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#define SMART_IDLE (0x2 << 3)
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#define REF_ON_IDLE (0x1 << 6)
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/* UART */
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#define OMAP2420_UART1 0x4806A000
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#define OMAP2420_UART2 0x4806C000
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#define OMAP2420_UART3 0x4806E000
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/* General Purpose Timers */
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#define OMAP2420_GPT1 0x48028000
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#define OMAP2420_GPT2 0x4802A000
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#define OMAP2420_GPT3 0x48078000
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#define OMAP2420_GPT4 0x4807A000
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#define OMAP2420_GPT5 0x4807C000
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#define OMAP2420_GPT6 0x4807E000
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#define OMAP2420_GPT7 0x48080000
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#define OMAP2420_GPT8 0x48082000
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#define OMAP2420_GPT9 0x48084000
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#define OMAP2420_GPT10 0x48086000
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#define OMAP2420_GPT11 0x48088000
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#define OMAP2420_GPT12 0x4808A000
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/* timer regs offsets (32 bit regs) */
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#define TIDR 0x0 /* r */
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#define TIOCP_CFG 0x10 /* rw */
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#define TISTAT 0x14 /* r */
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#define TISR 0x18 /* rw */
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#define TIER 0x1C /* rw */
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#define TWER 0x20 /* rw */
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#define TCLR 0x24 /* rw */
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#define TCRR 0x28 /* rw */
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#define TLDR 0x2C /* rw */
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#define TTGR 0x30 /* rw */
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#define TWPS 0x34 /* r */
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#define TMAR 0x38 /* rw */
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#define TCAR1 0x3c /* r */
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#define TSICR 0x40 /* rw */
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#define TCAR2 0x44 /* r */
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/* WatchDog Timers (1 secure, 3 GP) */
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#define WD1_BASE 0x48020000
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#define WD2_BASE 0x48022000
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#define WD3_BASE 0x48024000
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#define WD4_BASE 0x48026000
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#define WWPS 0x34 /* r */
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#define WSPR 0x48 /* rw */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* PRCM */
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#define OMAP2420_CM_BASE 0x48008000
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#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
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#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140)
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#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200)
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#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204)
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#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210)
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#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214)
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#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240)
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#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440)
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#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244)
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#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340)
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#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)
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#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500)
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#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520)
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#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540)
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#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544)
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#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840)
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/*
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* H4 specific Section
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*/
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/*
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* The 2420's chip selects are programmable. The mask ROM
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* does configure CS0 to 0x08000000 before dispatch. So, if
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* you want your code to live below that address, you have to
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* be prepared to jump though hoops, to reset the base address.
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*/
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#if defined(CONFIG_OMAP2420H4)
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/* GPMC */
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#ifdef CONFIG_VIRTIO_A /* Pre version B */
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# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
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# define H4_CS1_BASE 0x04000000 /* debug board */
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# define H4_CS2_BASE 0x0A000000 /* wifi board */
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#else
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# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
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# define H4_CS1_BASE 0x04000000 /* debug board */
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# define H4_CS2_BASE 0x0C000000 /* wifi board */
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#endif
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_OFFSET0 0x40000000
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#define SRAM_OFFSET1 0x00200000
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#define SRAM_OFFSET2 0x0000F800
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#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
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/* FPGA on Debug board.*/
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#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
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#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
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#endif /* endif CONFIG_2420H4 */
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/* Common */
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#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
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#define PERIFERAL_PORT_BASE 0x480FE003
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#endif
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