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https://github.com/brain-hackers/u-boot-brain
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2efef4041f
UART3 RX and TX pins are now moved to support uart download capability on the platform. Old pins are now GPIOs routed to expansion ports. All original boards should either have been returned for modifications or already modified for the required change and maintaining compatibility for older boards are no longer needed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
56 lines
2.1 KiB
C
56 lines
2.1 KiB
C
/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Author: Felipe Balbi <balbi@ti.com>
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*
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* Based on board/ti/dra7xx/evm.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MUX_DATA_BEAGLE_X15_H_
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#define _MUX_DATA_BEAGLE_X15_H_
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#include <asm/arch/mux_dra7xx.h>
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const struct pad_conf_entry core_padconf_array_essential[] = {
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{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
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{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
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{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
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{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
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{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
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{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
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{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
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{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
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{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
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{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
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{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
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{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
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{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
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{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
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{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
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{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
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{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
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{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
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{UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */
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{UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */
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{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
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{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
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{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
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{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
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{RGMII0_TXC, (M0) },
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{RGMII0_TXCTL, (M0) },
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{RGMII0_TXD3, (M0) },
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{RGMII0_TXD2, (M0) },
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{RGMII0_TXD1, (M0) },
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{RGMII0_TXD0, (M0) },
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{RGMII0_RXC, (IEN | M0) },
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{RGMII0_RXCTL, (IEN | M0) },
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{RGMII0_RXD3, (IEN | M0) },
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{RGMII0_RXD2, (IEN | M0) },
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{RGMII0_RXD1, (IEN | M0) },
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{RGMII0_RXD0, (IEN | M0) },
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{USB1_DRVVBUS, (M0 | FSC) },
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{SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
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};
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#endif /* _MUX_DATA_BEAGLE_X15_H_ */
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