mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-10 20:23:54 +09:00
f8f09dd404
bad_cache_range actually returned true if the range was OK, but it was used according to its name, which resulted in all valid dcache range invalidate/flush operations being dropped. Hence, most DMA transfers resulted in garbage data. This patch renames this function according to what it does, and it fixes the interpretation of its return value by other functions. The chosen naming is the same as for ARM926EJ-S in order to be consistent. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Stefano Babic <sbabic@denx.de>
175 lines
3.7 KiB
C
175 lines
3.7 KiB
C
/*
|
|
* (C) Copyright 2004 Texas Insturments
|
|
*
|
|
* (C) Copyright 2002
|
|
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
|
* Marius Groeger <mgroeger@sysgo.de>
|
|
*
|
|
* (C) Copyright 2002
|
|
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
/*
|
|
* CPU specific code
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <command.h>
|
|
#include <asm/system.h>
|
|
|
|
static void cache_flush(void);
|
|
|
|
int cleanup_before_linux (void)
|
|
{
|
|
/*
|
|
* this function is called just before we call linux
|
|
* it prepares the processor for linux
|
|
*
|
|
* we turn off caches etc ...
|
|
*/
|
|
|
|
disable_interrupts ();
|
|
|
|
#ifdef CONFIG_LCD
|
|
{
|
|
extern void lcd_disable(void);
|
|
extern void lcd_panel_disable(void);
|
|
|
|
lcd_disable(); /* proper disable of lcd & panel */
|
|
lcd_panel_disable();
|
|
}
|
|
#endif
|
|
|
|
/* turn off I/D-cache */
|
|
icache_disable();
|
|
dcache_disable();
|
|
/* flush I/D-cache */
|
|
cache_flush();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cache_flush(void)
|
|
{
|
|
unsigned long i = 0;
|
|
/* clean entire data cache */
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
|
|
/* invalidate both caches and flush btb */
|
|
asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
|
|
/* mem barrier to sync things */
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
|
|
}
|
|
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
|
|
#ifndef CONFIG_SYS_CACHELINE_SIZE
|
|
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
#endif
|
|
|
|
void invalidate_dcache_all(void)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
|
|
}
|
|
|
|
static int check_cache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
int ok = 1;
|
|
|
|
if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
|
|
ok = 0;
|
|
|
|
if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
|
|
ok = 0;
|
|
|
|
if (!ok)
|
|
debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
|
|
start, stop);
|
|
|
|
return ok;
|
|
}
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
if (!check_cache_range(start, stop))
|
|
return;
|
|
|
|
while (start < stop) {
|
|
asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
}
|
|
}
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
if (!check_cache_range(start, stop))
|
|
return;
|
|
|
|
while (start < stop) {
|
|
asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
|
|
start += CONFIG_SYS_CACHELINE_SIZE;
|
|
}
|
|
|
|
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
|
|
}
|
|
|
|
void flush_cache(unsigned long start, unsigned long size)
|
|
{
|
|
flush_dcache_range(start, start + size);
|
|
}
|
|
|
|
void enable_caches(void)
|
|
{
|
|
#ifndef CONFIG_SYS_ICACHE_OFF
|
|
icache_enable();
|
|
#endif
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
dcache_enable();
|
|
#endif
|
|
}
|
|
|
|
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
|
|
void invalidate_dcache_all(void)
|
|
{
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
}
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
}
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
{
|
|
}
|
|
|
|
void flush_cache(unsigned long start, unsigned long size)
|
|
{
|
|
}
|
|
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
|