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https://github.com/brain-hackers/u-boot-brain
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6752da6b26
The dram initialization sequence should be in order. This patch add mb for the dram intialization code to make sure the compiler do not disorder the code. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
154 lines
3.7 KiB
C
154 lines
3.7 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/immap.h>
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#include <netdev.h>
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#include <asm/io.h>
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale MCF5253 DEMO\n");
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return 0;
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};
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phys_size_t initdram(int board_type)
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{
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u32 dramsize = 0;
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
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u32 RC, temp;
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RC = (CONFIG_SYS_CLK / 1000000) >> 1;
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RC = (RC * 15) >> 4;
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/* Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
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__asm__("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x00003224);
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__asm__("nop");
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/* Initialize DMR0 */
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dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
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temp = (dramsize - 1) & 0xFFFC0000;
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mbar_writeLong(MCFSIM_DMR0, temp | 1);
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__asm__("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
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mb();
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__asm__("nop");
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/* Write to this block to initiate precharge */
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*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
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mb();
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__asm__("nop");
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/* Set RE bit in DACR */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x8000);
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__asm__("nop");
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/* Wait for at least 8 auto refresh cycles to occur */
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udelay(500);
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x0040);
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__asm__("nop");
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*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
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mb();
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}
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return dramsize;
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}
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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#ifdef CONFIG_CMD_IDE
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#include <ata.h>
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int ide_preinit(void)
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{
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return (0);
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}
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void ide_set_reset(int idereset)
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{
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volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
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long period;
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/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
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int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
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{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
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{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
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{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
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{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
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};
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if (idereset) {
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ata->cr = 0; /* control reset */
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udelay(100);
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} else {
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mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
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#define CALC_TIMING(t) (t + period - 1) / period
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period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
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/*ata->ton = CALC_TIMING (180); */
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ata->t1 = CALC_TIMING(piotms[2][0]);
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ata->t2w = CALC_TIMING(piotms[2][1]);
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ata->t2r = CALC_TIMING(piotms[2][1]);
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ata->ta = CALC_TIMING(piotms[2][8]);
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ata->trd = CALC_TIMING(piotms[2][7]);
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ata->t4 = CALC_TIMING(piotms[2][3]);
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ata->t9 = CALC_TIMING(piotms[2][6]);
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ata->cr = 0x40; /* IORDY enable */
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udelay(2000);
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ata->cr |= 0x01; /* IORDY enable */
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}
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}
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#endif /* CONFIG_CMD_IDE */
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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