mirror of
https://github.com/brain-hackers/u-boot-brain
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238 lines
5.6 KiB
C
238 lines
5.6 KiB
C
/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* MCF5282 additionals
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* (C) Copyright 2005
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* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#ifdef CONFIG_M5271
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#include <asm/immap_5271.h>
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#include <asm/m5271.h>
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#endif
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#ifdef CONFIG_M5272
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#include <asm/immap_5272.h>
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#include <asm/m5272.h>
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#endif
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#ifdef CONFIG_M5282
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#include <asm/m5282.h>
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#include <asm/immap_5282.h>
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#endif
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#ifdef CONFIG_M5249
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#include <asm/m5249.h>
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#endif
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#ifdef CONFIG_M5271
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/*
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* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
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* determine which one we are running on, based on the Chip Identification
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* Register (CIR).
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*/
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int checkcpu (void)
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{
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char buf[32];
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unsigned short cir; /* Chip Identification Register */
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unsigned short pin; /* Part identification number */
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unsigned char prn; /* Part revision number */
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char *cpu_model;
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cir = mbar_readShort(MCF_CCM_CIR);
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pin = cir >> MCF_CCM_CIR_PIN_LEN;
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prn = cir & MCF_CCM_CIR_PRN_MASK;
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switch (pin) {
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case MCF_CCM_CIR_PIN_MCF5270:
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cpu_model = "5270";
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break;
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case MCF_CCM_CIR_PIN_MCF5271:
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cpu_model = "5271";
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break;
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default:
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cpu_model = NULL;
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break;
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}
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if (cpu_model)
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printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
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cpu_model, prn, strmhz(buf, CFG_CLK));
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else
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printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
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" (PIN: 0x%x) rev. %hu, at %s MHz\n",
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pin, prn, strmhz(buf, CFG_CLK));
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return 0;
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}
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
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mbar_writeByte(MCF_RCM_RCR,
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MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset (void)
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{
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mbar_writeShort(MCF_WTM_WSR, 0x5555);
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mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
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}
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int watchdog_disable (void)
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{
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mbar_writeShort(MCF_WTM_WCR, 0);
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return (0);
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}
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int watchdog_init (void)
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{
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mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif
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#ifdef CONFIG_M5272
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
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volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR);
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wdp->wdog_wrrr = 0;
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udelay (1000);
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/* enable watchdog, set timeout to 0 and wait */
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wdp->wdog_wrrr = 1;
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while (1);
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/* we don't return! */
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return 0;
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};
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int checkcpu(void) {
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ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR);
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uchar msk;
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char *suf;
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puts ("CPU: ");
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msk = (*dirp > 28) & 0xf;
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switch (msk) {
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case 0x2: suf = "1K75N"; break;
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case 0x4: suf = "3K75N"; break;
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default:
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suf = NULL;
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printf ("Freescale MCF5272 (Mask:%01x)\n", msk);
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break;
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}
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if (suf)
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printf ("Freescale MCF5272 %s\n", suf);
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset (void)
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{
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volatile immap_t * regp = (volatile immap_t *)CFG_MBAR;
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regp->wdog_reg.wdog_wcr = 0;
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}
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int watchdog_disable (void)
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{
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volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
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regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
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regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
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regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */
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puts ("WATCHDOG:disabled\n");
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return (0);
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}
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int watchdog_init (void)
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{
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volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
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regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
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/* set timeout and enable watchdog */
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regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
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regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
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puts ("WATCHDOG:enabled\n");
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif /* #ifdef CONFIG_M5272 */
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#ifdef CONFIG_M5282
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int checkcpu (void)
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{
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unsigned char resetsource = MCFRESET_RSR;
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printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
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MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
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printf ("Reset:%s%s%s%s%s%s%s\n",
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(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
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(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
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(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
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(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
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(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
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(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
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(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""
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);
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return 0;
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}
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
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return 0;
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};
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#endif
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#ifdef CONFIG_M5249 /* test-only: todo... */
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int checkcpu (void)
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{
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char buf[32];
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printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK));
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return 0;
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}
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
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/* enable watchdog, set timeout to 0 and wait */
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mbar_writeByte(MCFSIM_SYPCR, 0xc0);
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while (1);
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/* we don't return! */
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return 0;
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};
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#endif
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