mirror of
https://github.com/brain-hackers/u-boot-brain
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f8cf3d1ebd
Some cache operations ({i|d}cache_{enable|disable|status} or
flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF
is set.
This is required for force disable of caches on early boot.
What if something was executed before U-boot and enabled caches
(low-level bootloaders, previously run kernel etc.)?
But if CPU doesn't really have caches any attempt to access
cache-related AUX registers triggers instruction error exception.
So for convenience we'll try to avoid exceptions by checking if CPU
actually has caches (we check separately data and instruction cache
existence) at all.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARC_ARCREGS_H
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#define _ASM_ARC_ARCREGS_H
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/*
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* ARC architecture has additional address space - auxiliary registers.
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* These registers are mostly used for configuration purposes.
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* These registers are not memory mapped and special commands are used for
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* access: "lr"/"sr".
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*/
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#define ARC_AUX_IDENTITY 0x04
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#define ARC_AUX_STATUS32 0x0a
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/* Instruction cache related auxiliary registers */
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#define ARC_AUX_IC_IVIC 0x10
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#define ARC_AUX_IC_CTRL 0x11
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#define ARC_AUX_IC_IVIL 0x19
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#if (CONFIG_ARC_MMU_VER > 2)
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#define ARC_AUX_IC_PTAG 0x1E
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#endif
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#define ARC_BCR_IC_BUILD 0x77
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/* Timer related auxiliary registers */
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#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
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#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
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#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
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#define ARC_AUX_INTR_VEC_BASE 0x25
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/* Data cache related auxiliary registers */
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#define ARC_AUX_DC_IVDC 0x47
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#define ARC_AUX_DC_CTRL 0x48
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#define ARC_AUX_DC_IVDL 0x4A
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#define ARC_AUX_DC_FLSH 0x4B
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#define ARC_AUX_DC_FLDL 0x4C
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#if (CONFIG_ARC_MMU_VER > 2)
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#define ARC_AUX_DC_PTAG 0x5C
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#endif
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#define ARC_BCR_DC_BUILD 0x72
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#ifndef __ASSEMBLY__
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/* Accessors for auxiliary registers */
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(reg_immed, val) \
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__builtin_arc_sr((unsigned int)val, reg_immed)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARC_ARCREGS_H */
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