mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
f8973325d0
The Calxeda Midway part has A15 cores, which do not have the Highbank A9's SCU used there for resetting the chip. Add code to distinguish between the A9 and the A15 and invoke the appropriate register writes to support the newer part. Andre: rework detection of Highbank vs. Midway Rob: fix Andre's reworked detection Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> Signed-off-by: Rob Herring <robh@kernel.org>
139 lines
2.6 KiB
C
139 lines
2.6 KiB
C
/*
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* Copyright 2010-2011 Calxeda, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ahci.h>
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#include <netdev.h>
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#include <scsi.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#define HB_AHCI_BASE 0xffe08000
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#define HB_SCU_A9_PWR_STATUS 0xfff10008
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#define HB_SREG_A9_PWR_REQ 0xfff3cf00
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#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
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#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
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#define HB_SREG_A15_PWR_CTRL 0xfff3c200
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#define HB_PWR_SUSPEND 0
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#define HB_PWR_SOFT_RESET 1
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#define HB_PWR_HARD_RESET 2
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#define HB_PWR_SHUTDOWN 3
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#define PWRDOM_STAT_SATA 0x80000000
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#define PWRDOM_STAT_PCI 0x40000000
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#define PWRDOM_STAT_EMMC 0x20000000
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#define HB_SCU_A9_PWR_NORMAL 0
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#define HB_SCU_A9_PWR_DORMANT 2
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#define HB_SCU_A9_PWR_OFF 3
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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icache_enable();
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return 0;
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}
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/* We know all the init functions have been run now */
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_CALXEDA_XGMAC
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rc += calxedaxgmac_initialize(0, 0xfff50000);
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rc += calxedaxgmac_initialize(1, 0xfff51000);
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#endif
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return rc;
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}
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#ifdef CONFIG_SCSI_AHCI_PLAT
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void scsi_init(void)
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{
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u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
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if (reg & PWRDOM_STAT_SATA) {
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ahci_init((void __iomem *)HB_AHCI_BASE);
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scsi_scan(1);
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}
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char envbuffer[16];
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u32 boot_choice;
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boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
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sprintf(envbuffer, "bootcmd%d", boot_choice);
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if (getenv(envbuffer)) {
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sprintf(envbuffer, "run bootcmd%d", boot_choice);
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setenv("bootcmd", envbuffer);
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} else
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setenv("bootcmd", "");
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return 0;
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = SZ_512M;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *fdt, bd_t *bd)
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{
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static const char disabled[] = "disabled";
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u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
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if (!(reg & PWRDOM_STAT_SATA))
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do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
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disabled, sizeof(disabled), 1);
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if (!(reg & PWRDOM_STAT_EMMC))
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do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
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disabled, sizeof(disabled), 1);
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return 0;
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}
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#endif
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static int is_highbank(void)
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{
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uint32_t midr;
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asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
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return (midr & 0xfff0) == 0xc090;
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}
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void reset_cpu(ulong addr)
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{
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writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
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if (is_highbank())
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writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
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else
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writel(0x1, HB_SREG_A15_PWR_CTRL);
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wfi();
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}
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