mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
38 lines
878 B
C
38 lines
878 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*/
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/* Tegra cache routines */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch/gp_padctrl.h>
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#ifndef CONFIG_ARM64
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void config_cache(void)
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{
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u32 reg = 0;
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/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #0x41\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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/* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
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if (tegra_get_chip() < CHIPID_TEGRA114)
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return;
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/*
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* Systems with an architectural L2 cache must not use the PL310.
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* Config L2CTLR here for a data RAM latency of 3 cycles.
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*/
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asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
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reg &= ~7;
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reg |= 2;
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asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
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}
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#endif
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