mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
123 lines
2.8 KiB
ArmAsm
123 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Secure entry function for CPU Core #1
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*
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* (C) Copyright 2016
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Harinarayan Bhatta <harinarayan@ti.com>
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*/
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#include <config.h>
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#include <asm/arch/omap.h>
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#include <asm/omap_common.h>
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#include <linux/linkage.h>
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.arch_extension sec
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#if !defined(CONFIG_SYS_DCACHE_OFF)
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.global flush_dcache_range
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#endif
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#define AUX_CORE_BOOT_0 0x48281800
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#define AUX_CORE_BOOT_1 0x48281804
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#ifdef CONFIG_DRA7XX
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/* DRA7xx ROM code function "startup_BootSlave". This function is where CPU1
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* waits on WFE, polling on AUX_CORE_BOOT_x registers.
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* This address is same for J6 and J6 Eco.
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*/
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#define ROM_FXN_STARTUP_BOOTSLAVE 0x00038a64
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#endif
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/* Assembly core where CPU1 is woken up into
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* No need to save-restore registers, does not use stack.
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*/
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LENTRY(cpu1_entry)
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ldr r4, =omap_smc_sec_cpu1_args
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ldm r4, {r0,r1,r2,r3} @ Retrieve args
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mov r6, #0xFF @ Indicate new Task call
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mov r12, #0x00 @ Secure Service ID in R12
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dsb
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dmb
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smc 0 @ SMC #0 to enter monitor mode
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b .Lend @ exit at end of the service execution
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nop
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@ In case of IRQ happening in Secure, then ARM will branch here.
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@ At that moment, IRQ will be pending and ARM will jump to Non Secure
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@ IRQ handler
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mov r12, #0xFE
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dsb
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dmb
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smc 0 @ SMC #0 to enter monitor mode
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.Lend:
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ldr r4, =omap_smc_sec_cpu1_args
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str r0, [r4, #0x10] @ save return value
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ldr r4, =AUX_CORE_BOOT_0
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mov r5, #0x0
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str r5, [r4]
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ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE
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sev @ Tell CPU0 we are done
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bx r4 @ Jump back to ROM
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END(cpu1_entry)
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/*
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* u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
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*
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* Makes a secure ROM/PPA call on CPU Core #1 on supported platforms.
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* Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by
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* u-boot.
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*/
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ENTRY(omap_smc_sec_cpu1)
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push {r4, r5, lr}
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ldr r4, =omap_smc_sec_cpu1_args
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stm r4, {r0,r1,r2,r3} @ Save args to memory
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#if !defined(CONFIG_SYS_DCACHE_OFF)
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mov r0, r4
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mov r1, #CONFIG_SYS_CACHELINE_SIZE
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add r1, r0, r1 @ dcache is not enabled on CPU1, so
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blx flush_dcache_range @ flush the cache on args buffer
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#endif
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ldr r4, =AUX_CORE_BOOT_1
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ldr r5, =cpu1_entry
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str r5, [r4] @ Setup CPU1 entry function
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ldr r4, =AUX_CORE_BOOT_0
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mov r5, #0x10
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str r5, [r4] @ Tell ROM to exit while loop
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sev @ Wake up CPU1
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.Lwait:
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wfe @ Wait for CPU1 to finish
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nop
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ldr r5, [r4] @ Check if CPU1 is done
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cmp r5, #0
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bne .Lwait
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ldr r4, =omap_smc_sec_cpu1_args
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ldr r0, [r4, #0x10] @ Retrieve return value
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pop {r4, r5, pc}
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ENDPROC(omap_smc_sec_cpu1)
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/*
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* Buffer to save function arguments and return value for omap_smc_sec_cpu1
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*/
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.section .data
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omap_smc_sec_cpu1_args:
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#if !defined(CONFIG_SYS_DCACHE_OFF)
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.balign CONFIG_SYS_CACHELINE_SIZE
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.rept CONFIG_SYS_CACHELINE_SIZE/4
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.word 0
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.endr
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#else
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.rept 5
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.word 0
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.endr
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#endif
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END(omap_smc_sec_cpu1_args)
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