mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
81 lines
1.7 KiB
C
81 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Common functions for OMAP4/5 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*/
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#include <common.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Without LPAE short descriptors are used
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* Set C - Cache Bit3
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* Set B - Buffer Bit2
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* The last 2 bits set to 0b10
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* Do Not set XN bit4
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* So value is 0xe
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*
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* With LPAE cache configuration happens via MAIR0 register
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* AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
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* 0xFF maps to Cache writeback with Read and Write Allocate set
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* The bits[1:0] should have the value 0b01 for the first level
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* descriptor.
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* So the value is 0xd
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*/
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#ifdef CONFIG_ARMV7_LPAE
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#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
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#else
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#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
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#endif
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#define ARMV7_DOMAIN_CLIENT 1
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#define ARMV7_DOMAIN_MASK (0x3 << 0)
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void enable_caches(void)
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{
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/* Enable I cache if not enabled */
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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void dram_bank_mmu_setup(int bank)
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{
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bd_t *bd = gd->bd;
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int i;
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u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
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u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
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u32 end = start + size;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = start; i < end; i++)
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set_section_dcache(i, ARMV7_DCACHE_POLICY);
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}
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void arm_init_domains(void)
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{
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u32 reg;
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reg = get_dacr();
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/*
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* Set DOMAIN to client access so that all permissions
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* set in pagetables are validated by the mmu.
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*/
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reg &= ~ARMV7_DOMAIN_MASK;
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reg |= ARMV7_DOMAIN_CLIENT;
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set_dacr(reg);
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}
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