mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
174 lines
4.6 KiB
C
174 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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#include <linux/mtd/omap_gpmc.h>
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#include <jffs2/load_kernel.h>
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const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_NOR)
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char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
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#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
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char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
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#elif defined(CONFIG_CMD_ONENAND)
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char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
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#else
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char gpmc_cs0_flash = -1;
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#endif
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#if defined(CONFIG_OMAP34XX)
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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writel(0x0, addr + 0x400); /* clear pos A */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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#endif
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void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
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u32 base, u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/* Enable the config */
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writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
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(1 << 6)), &cs->config7);
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sdelay(2000);
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}
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void set_gpmc_cs0(int flash_type)
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{
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const u32 *gpmc_regs;
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u32 base, size;
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#if defined(CONFIG_NOR)
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const u32 gpmc_regs_nor[GPMC_MAX_REG] = {
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STNOR_GPMC_CONFIG1,
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STNOR_GPMC_CONFIG2,
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STNOR_GPMC_CONFIG3,
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STNOR_GPMC_CONFIG4,
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STNOR_GPMC_CONFIG5,
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STNOR_GPMC_CONFIG6,
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STNOR_GPMC_CONFIG7
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};
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#endif
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#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
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const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
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M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6,
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0
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};
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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const u32 gpmc_regs_onenand[GPMC_MAX_REG] = {
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ONENAND_GPMC_CONFIG1,
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ONENAND_GPMC_CONFIG2,
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ONENAND_GPMC_CONFIG3,
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ONENAND_GPMC_CONFIG4,
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ONENAND_GPMC_CONFIG5,
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ONENAND_GPMC_CONFIG6,
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0
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};
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#endif
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switch (flash_type) {
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#if defined(CONFIG_NOR)
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case MTD_DEV_TYPE_NOR:
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gpmc_regs = gpmc_regs_nor;
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base = CONFIG_SYS_FLASH_BASE;
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size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
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((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
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((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
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((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
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GPMC_SIZE_16M)));
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break;
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#endif
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#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
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case MTD_DEV_TYPE_NAND:
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gpmc_regs = gpmc_regs_nand;
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base = CONFIG_SYS_NAND_BASE;
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size = GPMC_SIZE_16M;
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break;
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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case MTD_DEV_TYPE_ONENAND:
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gpmc_regs = gpmc_regs_onenand;
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base = CONFIG_SYS_ONENAND_BASE;
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size = GPMC_SIZE_128M;
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break;
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#endif
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default:
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/* disable the GPMC0 config set by ROM code */
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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return;
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}
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/* enable chip-select specific configurations */
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enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* global settings */
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writel(0x00000008, &gpmc_cfg->sysconfig);
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writel(0x00000000, &gpmc_cfg->irqstatus);
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writel(0x00000000, &gpmc_cfg->irqenable);
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/* disable timeout, set a safe reset value */
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writel(0x00001ff0, &gpmc_cfg->timeout_control);
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writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ?
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0x00000200 : 0x00000012, &gpmc_cfg->config);
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set_gpmc_cs0(gpmc_cs0_flash);
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}
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