mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
310 lines
8.8 KiB
C
310 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* clock_am33xx.c
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*
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* clocks for AM33XX based boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#define OSC (V_OSCK/1000000)
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struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
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struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
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const struct dpll_regs dpll_mpu_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x88,
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.cm_idlest_dpll = CM_WKUP + 0x20,
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.cm_clksel_dpll = CM_WKUP + 0x2C,
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.cm_div_m2_dpll = CM_WKUP + 0xA8,
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};
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const struct dpll_regs dpll_core_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x90,
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.cm_idlest_dpll = CM_WKUP + 0x5C,
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.cm_clksel_dpll = CM_WKUP + 0x68,
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.cm_div_m4_dpll = CM_WKUP + 0x80,
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.cm_div_m5_dpll = CM_WKUP + 0x84,
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.cm_div_m6_dpll = CM_WKUP + 0xD8,
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};
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const struct dpll_regs dpll_per_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x8C,
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.cm_idlest_dpll = CM_WKUP + 0x70,
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.cm_clksel_dpll = CM_WKUP + 0x9C,
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.cm_div_m2_dpll = CM_WKUP + 0xAC,
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};
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const struct dpll_regs dpll_ddr_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x94,
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.cm_idlest_dpll = CM_WKUP + 0x34,
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.cm_clksel_dpll = CM_WKUP + 0x40,
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.cm_div_m2_dpll = CM_WKUP + 0xA0,
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};
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const struct dpll_regs dpll_disp_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x98,
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.cm_idlest_dpll = CM_WKUP + 0x48,
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.cm_clksel_dpll = CM_WKUP + 0x54,
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.cm_div_m2_dpll = CM_WKUP + 0xA4,
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};
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struct dpll_params dpll_mpu_opp100 = {
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CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_core_opp100 = {
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1000, OSC-1, -1, -1, 10, 8, 4};
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const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
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{ /* 19.2 MHz */
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{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
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{150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
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{125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
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{625, 11, 1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 24 MHz */
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{25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
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{30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
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{100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
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{125, 2, 1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 25 MHz */
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{24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
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{144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */
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{32, 0, 1, -1, -1, -1, -1}, /* OPP TB */
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{40, 0, 1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 26 MHz */
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{300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
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{360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */
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{400, 12, 1, -1, -1, -1, -1}, /* OPP TB */
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{500, 12, 1, -1, -1, -1, -1} /* OPP NT */
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},
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};
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const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {
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{625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
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{125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
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{40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
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{500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
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};
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const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
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{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
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{384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
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{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
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};
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const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
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{505, 15, 2, -1, -1, -1, -1}, /*19.2*/
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{101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
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{303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
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{303, 12, 2, -1, -1, -1, -1} /* 26 MHz */
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};
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const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
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{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
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{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
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{16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
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{200, 12, 1, -1, -1, -1, -1} /* 26 MHz */
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};
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const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
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{665, 47, 1, -1, -1, -1, -1}, /*19.2*/
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{133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
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{266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
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{133, 12, 1, -1, -1, -1, -1} /* 26 MHz */
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};
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__weak const struct dpll_params *get_dpll_mpu_params(void)
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{
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return &dpll_mpu_opp100;
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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int ind = get_sys_clk_index();
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return &dpll_core_1000MHz[ind];
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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int ind = get_sys_clk_index();
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return &dpll_per_192MHz[ind];
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}
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void setup_clocks_for_console(void)
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{
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clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
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CD_CLKCTRL_CLKTRCTRL_SHIFT);
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clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
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CD_CLKCTRL_CLKTRCTRL_SHIFT);
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clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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clrsetbits_le32(&cmper->uart1clkctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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clrsetbits_le32(&cmper->uart2clkctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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clrsetbits_le32(&cmper->uart3clkctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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clrsetbits_le32(&cmper->uart4clkctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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clrsetbits_le32(&cmper->uart5clkctrl,
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MODULE_CLKCTRL_MODULEMODE_MASK,
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MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
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MODULE_CLKCTRL_MODULEMODE_SHIFT);
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}
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void enable_basic_clocks(void)
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{
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u32 *const clk_domains[] = {
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&cmper->l3clkstctrl,
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&cmper->l4fwclkstctrl,
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&cmper->l3sclkstctrl,
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&cmper->l4lsclkstctrl,
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&cmwkup->wkclkstctrl,
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&cmper->emiffwclkctrl,
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&cmrtc->clkstctrl,
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0
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};
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u32 *const clk_modules_explicit_en[] = {
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&cmper->l3clkctrl,
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&cmper->l4lsclkctrl,
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&cmper->l4fwclkctrl,
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&cmwkup->wkl4wkclkctrl,
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&cmper->l3instrclkctrl,
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&cmper->l4hsclkctrl,
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&cmwkup->wkgpio0clkctrl,
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&cmwkup->wkctrlclkctrl,
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&cmper->timer2clkctrl,
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&cmper->gpmcclkctrl,
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&cmper->elmclkctrl,
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&cmper->mmc0clkctrl,
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&cmper->mmc1clkctrl,
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&cmwkup->wkup_i2c0ctrl,
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&cmper->gpio1clkctrl,
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&cmper->gpio2clkctrl,
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&cmper->gpio3clkctrl,
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&cmper->i2c1clkctrl,
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&cmper->cpgmac0clkctrl,
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&cmper->spi0clkctrl,
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&cmrtc->rtcclkctrl,
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&cmper->usb0clkctrl,
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&cmper->emiffwclkctrl,
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&cmper->emifclkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
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/* Select the Master osc 24 MHZ as Timer2 clock source */
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writel(0x1, &cmdpll->clktimer2clk);
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}
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/*
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* Enable Spread Spectrum for the MPU by calculating the required
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* values and setting the registers accordingly.
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* @param permille The spreading in permille (10th of a percent)
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*/
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void set_mpu_spreadspectrum(int permille)
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{
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u32 multiplier_m;
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u32 predivider_n;
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u32 cm_clksel_dpll_mpu;
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u32 cm_clkmode_dpll_mpu;
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u32 ref_clock;
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u32 pll_bandwidth;
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u32 mod_freq_divider;
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u32 exponent;
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u32 mantissa;
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u32 delta_m_step;
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printf("Enabling Spread Spectrum of %d permille for MPU\n",
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permille);
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/* Read PLL parameter m and n */
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cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu);
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multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF;
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predivider_n = cm_clksel_dpll_mpu & 0x7F;
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/*
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* Calculate reference clock (clock after pre-divider),
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* its max. PLL bandwidth,
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* and resulting mod_freq_divider
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*/
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ref_clock = V_OSCK / (predivider_n + 1);
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pll_bandwidth = ref_clock / 70;
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mod_freq_divider = ref_clock / (4 * pll_bandwidth);
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/* Calculate Mantissa/Exponent */
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exponent = 0;
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mantissa = mod_freq_divider;
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while ((mantissa > 127) && (exponent < 7)) {
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exponent++;
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mantissa /= 2;
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}
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if (mantissa > 127)
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mantissa = 127;
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mod_freq_divider = mantissa << exponent;
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/*
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* Calculate Modulation steps
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* As we use Downspread only, the spread is twice the value of
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* permille, so Div2!
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* As it takes the value in percent, divide by ten!
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*/
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delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18;
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delta_m_step /= 100;
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delta_m_step /= mod_freq_divider;
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if (delta_m_step > 0xFFFFF)
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delta_m_step = 0xFFFFF;
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/* Setup Spread Spectrum */
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writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu);
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writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu);
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cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu);
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/* clear all SSC flags */
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cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT);
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/* enable SSC with Downspread only */
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cm_clkmode_dpll_mpu |= CM_CLKMODE_DPLL_SSC_EN_MASK |
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CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
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writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu);
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while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000))
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;
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}
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