Marek Vasut bfa89d2ba8 arm: socfpga: Fix FPGA bitstream programming routine ... In case the FPGA bitstream is aligned to 4 bytes, skip the part of the assembler which handles unaligned bitstream. Otherwise, that part will loop indefinitelly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>		2015-08-08 14:14:04 +02:00
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ACEX1K.c
altera.c
cyclon2.c
fpga.c
ivm_core.c
lattice.c
Makefile
socfpga.c	arm: socfpga: Fix FPGA bitstream programming routine	2015-08-08 14:14:04 +02:00
spartan2.c
spartan3.c
stratixII.c
virtex2.c
xilinx.c	fpga: xilinx: Show fpga info if defined	2015-01-21 10:25:43 +01:00
zynqpl.c