mirror of
https://github.com/brain-hackers/u-boot-brain
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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
39 lines
1.0 KiB
C
39 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Take from coreboot project file of the same name
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*/
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#ifndef _ASM_ARCH_SYSTEMAGENT_H
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#define _ASM_ARCH_SYSTEMAGENT_H
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/* Device 0:0.0 PCI configuration space */
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#include <linux/bitops.h>
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#define MCHBAR 0x48
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/* RAPL Package Power Limit register under MCHBAR */
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#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
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#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
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#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
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#define BIOS_RESET_CPL 0x7078
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#define PCODE_INIT_DONE BIT(8)
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#define MCHBAR_RAPL_PPL 0x70A8
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#define CORE_DISABLE_MASK 0x7168
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#define CAPID0_A 0xE4
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#define VTD_DISABLE BIT(23)
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#define DEFVTBAR 0x6c80
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#define GFXVTBAR 0x6c88
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#define VTBAR_ENABLED 0x01
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#define VTBAR_MASK GENMASK_ULL(39, 12)
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#define VTBAR_SIZE 0x1000
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/**
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* enable_bios_reset_cpl() - Tell the system agent that memory/power are ready
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*
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* This should be called when U-Boot has set up the memory and power
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* management.
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*/
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void enable_bios_reset_cpl(void);
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#endif
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