mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-14 22:23:56 +09:00
239 lines
4.8 KiB
C
239 lines
4.8 KiB
C
/*
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* Balloon3 Support
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <spartan3.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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void balloon3_init_fpga(void);
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* arch number of vpac270 */
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gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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/* Init the FPGA */
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balloon3_init_fpga();
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return 0;
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}
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struct serial_device *default_serial_console(void)
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{
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return &serial_stuart_device;
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}
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extern void pxa_dram_init(void);
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int dram_init(void)
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{
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pxa_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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}
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#ifdef CONFIG_CMD_USB
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int usb_board_init(void)
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{
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writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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;
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
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writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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/* enable port 2 */
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writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
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UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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return 0;
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}
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void usb_board_init_fail(void)
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{
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return;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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#endif
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#if defined(CONFIG_FPGA)
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/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
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int fpga_pgm_fn(int nassert, int nflush, int cookie)
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{
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if (nassert)
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writel(0x80, GPCR3);
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else
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writel(0x80, GPSR3);
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if (nflush)
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writel(0x100, GPCR3);
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else
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writel(0x100, GPSR3);
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return nassert;
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}
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/* Check GPIO83 -- INITB */
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int fpga_init_fn(int cookie)
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{
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return !(readl(GPLR2) & 0x80000);
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}
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/* Check GPIO84 -- BUSY */
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int fpga_busy_fn(int cookie)
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{
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return !(readl(GPLR2) & 0x100000);
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}
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/* Check GPIO111 -- DONE */
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int fpga_done_fn(int cookie)
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{
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return readl(GPLR3) & 0x8000;
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}
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/* Configure GPIO104 as GPIO and deassert it */
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int fpga_pre_config_fn(int cookie)
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{
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writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
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writel(0x100, GPCR3);
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return 0;
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}
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/* Configure GPIO104 as nSKTSEL */
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int fpga_post_config_fn(int cookie)
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{
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writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
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return 0;
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}
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/* Toggle RDnWR */
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int fpga_wr_fn(int nassert_write, int flush, int cookie)
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{
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udelay(1000);
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if (nassert_write)
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writel(0x100, GPCR3);
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else
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writel(0x100, GPSR3);
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return nassert_write;
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}
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/* Write program to the FPGA */
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int fpga_wdata_fn(uchar data, int flush, int cookie)
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{
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writeb(data, 0x10f00000);
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return 0;
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}
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/* Toggle Clock pin -- NO-OP */
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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return assert_clk;
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}
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/* Toggle ChipSelect pin -- NO-OP */
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int fpga_cs_fn(int assert_clk, int flush, int cookie)
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{
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return assert_clk;
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}
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Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_init_fn,
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NULL, /* err */
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fpga_done_fn,
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fpga_clk_fn,
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fpga_cs_fn,
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fpga_wr_fn,
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NULL, /* rdata */
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fpga_wdata_fn,
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fpga_busy_fn,
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NULL, /* abort */
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fpga_post_config_fn,
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};
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Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
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(void *)&balloon3_fpga_fns, 0);
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/* Initialize the FPGA */
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void balloon3_init_fpga(void)
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{
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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}
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#else
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void balloon3_init_fpga(void) {}
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#endif /* CONFIG_FPGA */
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