Samuel Mescoff f7cf291aa7 ARM: at91: sama5d2: configure the L2 cache memory ... The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>		2016-02-18 21:34:41 +01:00
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arm920t	ARM: at91: clock: add PLLB enable/disable functions	2016-02-18 21:34:41 +01:00
arm926ejs	ARM: at91: clock: add PLLB enable/disable functions	2016-02-18 21:34:41 +01:00
armv7	ARM: at91: armv7: clean up UTMI PLL handle code	2016-02-18 21:34:40 +01:00
include/mach	ARM: at91: sama5d2: configure the L2 cache memory	2016-02-18 21:34:41 +01:00
atmel_sfr.c	ARM: at91: sama5d2: configure the L2 cache memory	2016-02-18 21:34:41 +01:00
clock.c	ARM: at91: clock: add PMC_PLLICPR init function	2016-02-18 21:34:41 +01:00
config.mk	ARM: at91: collect SoC sources into mach-at91	2015-02-21 08:23:51 -05:00
Kconfig	arm: at91: Add support for DENX MA5D4 SoM and EVK	2016-02-18 21:34:41 +01:00
Makefile	ARM: at91: clock: add a new file to handle clock	2016-02-18 21:34:40 +01:00
matrix.c	arm: at91/spl: matrix: use matrix slave id macros	2015-11-30 22:27:54 +01:00
mpddrc.c	arm: at91/spl: mpddrc: use IP version to check configuration	2016-02-02 11:49:12 +01:00
phy.c	ARM: cpu: at91: clean up peripheral clock code	2016-02-18 21:34:40 +01:00
sdram.c	ARM: cpu: at91: clean up peripheral clock code	2016-02-18 21:34:40 +01:00
spl_at91.c	ARM: at91: clean up the PMC_PLLICPR init code	2016-02-18 21:34:41 +01:00
spl_atmel.c	ARM: at91: sama5d2: configure the L2 cache memory	2016-02-18 21:34:41 +01:00
spl.c	ARM: atmel: at91sam9x5ek: enable spl support	2015-04-01 01:04:31 +02:00