186 lines
3.6 KiB
C
186 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <syscon.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/boot_mode.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/periph.h>
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#include <asm/arch-rockchip/misc.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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__weak int rk_board_late_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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setup_boot_mode();
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return rk_board_late_init();
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}
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int board_init(void)
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{
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int ret;
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#ifdef CONFIG_DM_REGULATOR
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ret = regulators_enable_boot_on(false);
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if (ret)
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debug("%s: Cannot enable boot on regulator\n", __func__);
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#endif
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return 0;
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}
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#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_USB_GADGET)
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#include <usb.h>
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#if defined(CONFIG_USB_GADGET_DWC2_OTG)
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#include <usb/dwc2_udc.h>
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static struct dwc2_plat_otg_data otg_data = {
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.rx_fifo_sz = 512,
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.np_tx_fifo_sz = 16,
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.tx_fifo_sz = 128,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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ofnode node;
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const char *mode;
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bool matched = false;
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/* find the usb_otg node */
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node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
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while (ofnode_valid(node)) {
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mode = ofnode_read_string(node, "dr_mode");
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if (mode && strcmp(mode, "otg") == 0) {
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matched = true;
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break;
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}
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node = ofnode_by_compatible(node, "snps,dwc2");
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}
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if (!matched) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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otg_data.regs_otg = ofnode_get_addr(node);
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#ifdef CONFIG_ROCKCHIP_RK3288
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int ret;
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u32 phandle, offset;
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ofnode phy_node;
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ret = ofnode_read_u32(node, "phys", &phandle);
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if (ret)
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return ret;
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node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(node)) {
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debug("Not found usb phy device\n");
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return -ENODEV;
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}
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phy_node = ofnode_get_parent(node);
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if (!ofnode_valid(node)) {
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debug("Not found usb phy device\n");
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return -ENODEV;
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}
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otg_data.phy_of_node = phy_node;
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ret = ofnode_read_u32(node, "reg", &offset);
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if (ret)
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return ret;
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otg_data.regs_phy = offset +
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(u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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#endif
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return dwc2_udc_probe(&otg_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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#endif /* CONFIG_USB_GADGET_DWC2_OTG */
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#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
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#include <dwc3-uboot.h>
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static struct dwc3_device dwc3_device_data = {
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.maximum_speed = USB_SPEED_HIGH,
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.base = 0xfe800000,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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.dis_u2_susphy_quirk = 1,
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.hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
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};
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int usb_gadget_handle_interrupts(void)
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{
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dwc3_uboot_handle_interrupt(0);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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return dwc3_uboot_init(&dwc3_device_data);
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}
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#endif /* CONFIG_USB_DWC3_GADGET */
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#endif /* CONFIG_USB_GADGET */
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#if CONFIG_IS_ENABLED(FASTBOOT)
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int fastboot_set_reboot_flag(void)
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{
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printf("Setting reboot to fastboot flag ...\n");
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/* Set boot mode to fastboot */
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writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
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return 0;
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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__weak int misc_init_r(void)
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{
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const u32 cpuid_offset = 0x7;
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const u32 cpuid_length = 0x10;
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u8 cpuid[cpuid_length];
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int ret;
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ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
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if (ret)
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return ret;
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ret = rockchip_cpuid_set(cpuid, cpuid_length);
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if (ret)
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return ret;
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ret = rockchip_setup_macaddr();
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return ret;
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}
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#endif
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