131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <log.h>
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#include <asm/arch-fsl-layerscape/immap_lsch3.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <asm/arch-fsl-layerscape/fsl_portals.h>
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struct icid_id_table icid_tbl[] = {
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SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
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SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
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SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
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SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
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SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
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SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
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SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
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SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
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SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
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#ifdef CONFIG_FSL_CAAM
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SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
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SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
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SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
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SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
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SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
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SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
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#endif
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};
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int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
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/* integrated PCI is handled separately as it's not part of CCSR/SCFG */
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#ifdef CONFIG_PCIE_ECAM_GENERIC
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#define ECAM_IERB_BASE 0x1f0800000ULL
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#define ECAM_IERB_OFFSET_NA -1
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#define ECAM_IERB_FUNC_CNT ARRAY_SIZE(ierb_offset)
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/* cache related transaction attributes for PCIe functions */
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#define ECAM_IERB_MSICAR (ECAM_IERB_BASE + 0xa400)
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#define ECAM_IERB_MSICAR_VALUE 0x30
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/* offset of IERB config register per PCI function */
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static int ierb_offset[] = {
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0x0800,
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0x1800,
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0x2800,
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0x3800,
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0x4800,
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0x5800,
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0x6800,
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ECAM_IERB_OFFSET_NA,
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0x0804,
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0x0808,
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0x1804,
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0x1808,
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};
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/*
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* Use a custom function for LS1028A, for now this is the only SoC with IERB
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* and we're currently considering reorganizing IERB for future SoCs.
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*/
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void set_ecam_icids(void)
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{
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int i;
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out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
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for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
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if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
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continue;
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out_le32(ECAM_IERB_BASE + ierb_offset[i],
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FSL_ECAM_STREAM_ID_START + i);
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}
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}
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static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
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const char *name, uint32_t idx, u32 val)
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{
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val = cpu_to_be32(val);
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return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
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strlen(name),
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idx * sizeof(val), &val,
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sizeof(val));
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}
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static int fdt_getprop_len(void *fdt, int nodeoffset, const char *name)
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{
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int len;
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if (fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), &len))
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return len;
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return 0;
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}
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void fdt_fixup_ecam(void *blob)
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{
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int off;
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off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
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if (off < 0) {
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debug("ECAM node not found\n");
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return;
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}
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if (fdt_getprop_len(blob, off, "msi-map") != 16 ||
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fdt_getprop_len(blob, off, "iommu-map") != 16) {
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log_err("invalid msi/iommu-map propertly size in ECAM node\n");
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return;
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}
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fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 2,
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FSL_ECAM_STREAM_ID_START);
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fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 3,
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ECAM_IERB_FUNC_CNT);
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fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 2,
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FSL_ECAM_STREAM_ID_START);
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fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 3,
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ECAM_IERB_FUNC_CNT);
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}
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#endif /* CONFIG_PCIE_ECAM_GENERIC */
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