421 lines
10 KiB
C
421 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#ifdef CONFIG_SYS_FSL_SRDS_1
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static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret = 0;
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#ifdef CONFIG_SYS_FSL_SRDS_1
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if (!serdes1_prtcl_map[NONE])
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fsl_serdes_init();
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ret |= serdes1_prtcl_map[device];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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if (!serdes2_prtcl_map[NONE])
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fsl_serdes_init();
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ret |= serdes2_prtcl_map[device];
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#endif
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return !!ret;
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}
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 cfg = gur_in32(&gur->rcwsr[4]);
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int i;
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switch (sd) {
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#ifdef CONFIG_SYS_FSL_SRDS_1
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case FSL_SRDS_1:
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cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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case FSL_SRDS_2:
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cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
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cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
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break;
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#endif
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default:
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printf("invalid SerDes%d\n", sd);
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break;
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}
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/* Is serdes enabled at all? */
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if (unlikely(cfg == 0))
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return -ENODEV;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_get_prtcl(sd, cfg, i) == device)
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return i;
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}
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return -ENODEV;
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}
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int get_serdes_protocol(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 cfg = gur_in32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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return cfg;
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}
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const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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default:
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return "100";
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}
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}
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void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
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u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 cfg;
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int lane;
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if (serdes_prtcl_map[NONE])
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return;
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memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
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cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
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cfg >>= sd_prctl_shift;
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printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
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if (!is_serdes_prtcl_valid(sd, cfg))
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printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
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if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
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debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
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else
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serdes_prtcl_map[lane_prtcl] = 1;
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}
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/* Set the first element to indicate serdes has been initialized */
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serdes_prtcl_map[NONE] = 1;
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}
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__weak int get_serdes_volt(void)
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{
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return -1;
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}
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__weak int set_serdes_volt(int svdd)
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{
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return -1;
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}
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int setup_serdes_volt(u32 svdd)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_serdes *serdes1_base;
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#ifdef CONFIG_SYS_FSL_SRDS_2
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struct ccsr_serdes *serdes2_base;
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#endif
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u32 cfg_rcw4 = gur_in32(&gur->rcwsr[4]);
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u32 cfg_rcw5 = gur_in32(&gur->rcwsr[5]);
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u32 cfg_tmp, reg = 0;
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int svdd_cur, svdd_tar;
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int ret;
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int i;
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/* Only support switch SVDD to 900mV/1000mV */
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if (svdd != 900 && svdd != 1000)
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return -EINVAL;
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svdd_tar = svdd;
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svdd_cur = get_serdes_volt();
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if (svdd_cur < 0)
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return -EINVAL;
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debug("%s: current SVDD: %dmV; target SVDD: %dmV\n",
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__func__, svdd_cur, svdd_tar);
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if (svdd_cur == svdd_tar)
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return 0;
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serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
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#ifdef CONFIG_SYS_FSL_SRDS_2
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serdes2_base = (void *)serdes1_base + 0x10000;
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#endif
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/* Put the all enabled lanes in reset */
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#ifdef CONFIG_SYS_FSL_SRDS_1
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cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
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reg = in_be32(&serdes1_base->lane[i].gcr0);
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reg &= 0xFF9FFFFF;
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out_be32(&serdes1_base->lane[i].gcr0, reg);
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}
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
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cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
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for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
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reg = in_be32(&serdes2_base->lane[i].gcr0);
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reg &= 0xFF9FFFFF;
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out_be32(&serdes2_base->lane[i].gcr0, reg);
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}
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#endif
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/* Put the all enabled PLL in reset */
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#ifdef CONFIG_SYS_FSL_SRDS_1
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cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
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for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg &= 0xFFFFFFBF;
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reg |= 0x10000000;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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udelay(1);
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg &= 0xFFFFFF1F;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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}
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udelay(1);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
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for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg &= 0xFFFFFFBF;
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reg |= 0x10000000;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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udelay(1);
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg &= 0xFFFFFF1F;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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}
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udelay(1);
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#endif
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/* Put the Rx/Tx calibration into reset */
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#ifdef CONFIG_SYS_FSL_SRDS_1
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reg = in_be32(&serdes1_base->srdstcalcr);
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reg &= 0xF7FFFFFF;
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out_be32(&serdes1_base->srdstcalcr, reg);
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reg = in_be32(&serdes1_base->srdsrcalcr);
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reg &= 0xF7FFFFFF;
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out_be32(&serdes1_base->srdsrcalcr, reg);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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reg = in_be32(&serdes2_base->srdstcalcr);
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reg &= 0xF7FFFFFF;
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out_be32(&serdes2_base->srdstcalcr, reg);
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reg = in_be32(&serdes2_base->srdsrcalcr);
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reg &= 0xF7FFFFFF;
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out_be32(&serdes2_base->srdsrcalcr, reg);
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#endif
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/*
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* If SVDD set failed, will not return directly, so that the
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* serdes lanes can complete reseting.
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*/
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ret = set_serdes_volt(svdd_tar);
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if (ret)
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printf("%s: Failed to set SVDD\n", __func__);
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/* Wait for SVDD to stabilize */
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udelay(100);
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/* For each PLL that’s not disabled via RCW */
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#ifdef CONFIG_SYS_FSL_SRDS_1
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cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
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for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg |= 0x00000020;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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udelay(1);
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg |= 0x00000080;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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/* Take the Rx/Tx calibration out of reset */
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if (!(cfg_tmp == 0x3 && i == 1)) {
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udelay(1);
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reg = in_be32(&serdes1_base->srdstcalcr);
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reg |= 0x08000000;
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out_be32(&serdes1_base->srdstcalcr, reg);
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reg = in_be32(&serdes1_base->srdsrcalcr);
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reg |= 0x08000000;
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out_be32(&serdes1_base->srdsrcalcr, reg);
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}
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}
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udelay(1);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
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for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg |= 0x00000020;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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udelay(1);
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg |= 0x00000080;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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/* Take the Rx/Tx calibration out of reset */
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if (!(cfg_tmp == 0x3 && i == 1)) {
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udelay(1);
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reg = in_be32(&serdes2_base->srdstcalcr);
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reg |= 0x08000000;
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out_be32(&serdes2_base->srdstcalcr, reg);
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reg = in_be32(&serdes2_base->srdsrcalcr);
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reg |= 0x08000000;
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out_be32(&serdes2_base->srdsrcalcr, reg);
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}
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}
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udelay(1);
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#endif
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/* Wait for at lesat 625us to ensure the PLLs being reset are locked */
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udelay(800);
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#ifdef CONFIG_SYS_FSL_SRDS_1
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cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
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for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
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/* if the PLL is not locked, set RST_ERR */
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reg = in_be32(&serdes1_base->bank[i].pllcr0);
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if (!((reg >> 23) & 0x1)) {
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg |= 0x20000000;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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} else {
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udelay(1);
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg &= 0xFFFFFFEF;
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reg |= 0x00000040;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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udelay(1);
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
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for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
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reg = in_be32(&serdes2_base->bank[i].pllcr0);
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if (!((reg >> 23) & 0x1)) {
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg |= 0x20000000;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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} else {
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udelay(1);
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg &= 0xFFFFFFEF;
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reg |= 0x00000040;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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udelay(1);
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}
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}
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#endif
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/* Take the all enabled lanes out of reset */
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#ifdef CONFIG_SYS_FSL_SRDS_1
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cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
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reg = in_be32(&serdes1_base->lane[i].gcr0);
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reg |= 0x00600000;
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out_be32(&serdes1_base->lane[i].gcr0, reg);
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}
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
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cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
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for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
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reg = in_be32(&serdes2_base->lane[i].gcr0);
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reg |= 0x00600000;
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out_be32(&serdes2_base->lane[i].gcr0, reg);
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}
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#endif
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/* For each PLL being reset, and achieved PLL lock set RST_DONE */
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#ifdef CONFIG_SYS_FSL_SRDS_1
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cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
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for (i = 0; i < 2; i++) {
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reg = in_be32(&serdes1_base->bank[i].pllcr0);
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if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
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reg = in_be32(&serdes1_base->bank[i].rstctl);
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reg |= 0x40000000;
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out_be32(&serdes1_base->bank[i].rstctl, reg);
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
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for (i = 0; i < 2; i++) {
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reg = in_be32(&serdes2_base->bank[i].pllcr0);
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if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
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reg = in_be32(&serdes2_base->bank[i].rstctl);
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reg |= 0x40000000;
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out_be32(&serdes2_base->bank[i].rstctl, reg);
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}
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}
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#endif
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return ret;
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}
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void fsl_serdes_init(void)
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{
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#ifdef CONFIG_SYS_FSL_SRDS_1
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serdes_init(FSL_SRDS_1,
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CONFIG_SYS_FSL_SERDES_ADDR,
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
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serdes1_prtcl_map);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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serdes_init(FSL_SRDS_2,
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CONFIG_SYS_FSL_SERDES_ADDR,
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FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
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FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
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serdes2_prtcl_map);
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#endif
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}
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