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![Stefano Babic](/assets/img/avatar_default.png)
The actual SPI driver for i.MX31 and i.MX51 controller use a wrong byte ordering, because it is supposed to work only with Freescale's devices, as the Power Controllers (PMIC). The driver is not suitable for general purposes, because the buffers passed to spi_xfer must be 32-bit aligned, as it is used mainly to send integer to PMIC devices. The patch drops any kind of limitation and makes the driver useful with devices controlled sending commands composed by single bytes (or by a odd number of bytes), such as spi flash, sensor, etc. Because the byte ordering is changed, any current driver using this controller must be adapted, too. Signed-off-by: Stefano Babic <sbabic@denx.de>
522 lines
12 KiB
C
522 lines
12 KiB
C
/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <mxc_gpio.h>
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#ifdef CONFIG_MX27
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/* i.MX27 has a completely wrong register layout and register definitions in the
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* datasheet, the correct one is in the Freescale's Linux driver */
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#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
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"See linux mxc_spi driver from Freescale for details."
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#elif defined(CONFIG_MX31)
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#include <asm/arch/mx31.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x10
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#define MXC_CSPISTAT 0x14
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#define MXC_CSPIPERIOD 0x18
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#define MXC_CSPITEST 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 8)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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static unsigned long spi_bases[] = {
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0x43fa4000,
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0x50010000,
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0x53f84000,
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};
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#elif defined(CONFIG_MX51)
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPICON 0x0C
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#define MXC_CSPIINT 0x10
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#define MXC_CSPIDMA 0x14
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#define MXC_CSPISTAT 0x18
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#define MXC_CSPIPERIOD 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_POL 4
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#define MXC_CSPICON_PHA 0
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#define MXC_CSPICON_SSPOL 12
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static unsigned long spi_bases[] = {
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CSPI1_BASE_ADDR,
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CSPI2_BASE_ADDR,
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CSPI3_BASE_ADDR,
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};
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#else
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#error "Unsupported architecture"
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#endif
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#define OUT MXC_GPIO_DIRECTION_OUT
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struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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u32 ctrl_reg;
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#if defined(CONFIG_MX51)
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u32 cfg_reg;
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#endif
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int gpio;
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int ss_pol;
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};
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static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxc_spi_slave, slave);
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}
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static inline u32 reg_read(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static inline void reg_write(unsigned long addr, u32 val)
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{
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*(volatile unsigned long*)addr = val;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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if (mxcs->gpio > 0)
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mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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if (mxcs->gpio > 0)
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mxc_gpio_set(mxcs->gpio,
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!(mxcs->ss_pol));
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}
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#ifdef CONFIG_MX51
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static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
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s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
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u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
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if (max_hz == 0) {
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printf("Error: desired clock is 0\n");
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return -1;
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}
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reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
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/* Reset spi */
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reg_write(mxcs->base + MXC_CSPICTRL, 0);
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reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
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/*
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* The following computation is taken directly from Freescale's code.
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*/
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if (clk_src > max_hz) {
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pre_div = clk_src / max_hz;
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if (pre_div > 16) {
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post_div = pre_div / 16;
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pre_div = 15;
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}
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if (post_div != 0) {
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for (i = 0; i < 16; i++) {
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if ((1 << i) >= post_div)
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break;
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}
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if (i == 16) {
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printf("Error: no divider for the freq: %d\n",
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max_hz);
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return -1;
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}
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post_div = i;
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}
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}
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debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
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MXC_CSPICTRL_SELCHAN(cs);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
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MXC_CSPICTRL_PREDIV(pre_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
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MXC_CSPICTRL_POSTDIV(post_div);
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/* always set to master mode */
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reg_ctrl |= 1 << (cs + 4);
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/* We need to disable SPI before changing registers */
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reg_ctrl &= ~MXC_CSPICTRL_EN;
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if (mode & SPI_CS_HIGH)
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ss_pol = 1;
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if (mode & SPI_CPOL)
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sclkpol = 1;
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if (mode & SPI_CPHA)
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sclkpha = 1;
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reg_config = reg_read(mxcs->base + MXC_CSPICON);
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/*
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* Configuration register setup
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* The MX51 has support different setup for each SS
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*/
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
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(ss_pol << (cs + MXC_CSPICON_SSPOL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
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(sclkpol << (cs + MXC_CSPICON_POL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
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(sclkpha << (cs + MXC_CSPICON_PHA));
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debug("reg_ctrl = 0x%x\n", reg_ctrl);
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reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl);
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debug("reg_config = 0x%x\n", reg_config);
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reg_write(mxcs->base + MXC_CSPICON, reg_config);
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/* save config register and control register */
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mxcs->ctrl_reg = reg_ctrl;
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mxcs->cfg_reg = reg_config;
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/* clear interrupt reg */
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reg_write(mxcs->base + MXC_CSPIINT, 0);
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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return 0;
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}
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#endif
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int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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const u8 *dout, u8 *din, unsigned long flags)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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int nbytes = (bitlen + 7) / 8;
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u32 data, cnt, i;
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debug("%s: bitlen %d dout 0x%x din 0x%x\n",
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__func__, bitlen, (u32)dout, (u32)din);
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mxcs->ctrl_reg = (mxcs->ctrl_reg &
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~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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#ifdef CONFIG_MX51
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reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg);
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#endif
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/* Clear interrupt register */
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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/*
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* The SPI controller works only with words,
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* check if less than a word is sent.
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* Access to the FIFO is only 32 bit
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*/
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if (bitlen % 32) {
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data = 0;
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cnt = (bitlen % 32) / 8;
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if (dout) {
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for (i = 0; i < cnt; i++) {
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data = (data << 8) | (*dout++ & 0xFF);
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}
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(mxcs->base + MXC_CSPITXDATA, data);
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nbytes -= cnt;
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}
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data = 0;
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while (nbytes > 0) {
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data = 0;
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if (dout) {
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/* Buffer is not 32-bit aligned */
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if ((unsigned long)dout & 0x03) {
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data = 0;
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for (i = 0; i < 4; i++, data <<= 8) {
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data = (data << 8) | (*dout++ & 0xFF);
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}
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} else {
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data = *(u32 *)dout;
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data = cpu_to_be32(data);
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}
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dout += 4;
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(mxcs->base + MXC_CSPITXDATA, data);
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nbytes -= 4;
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}
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/* FIFO is written, now starts the transfer setting the XCH bit */
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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/* Wait until the TC (Transfer completed) bit is set */
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while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0)
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;
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/* Transfer completed, clear any pending request */
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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nbytes = (bitlen + 7) / 8;
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cnt = nbytes % 32;
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if (bitlen % 32) {
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data = reg_read(mxcs->base + MXC_CSPIRXDATA);
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cnt = (bitlen % 32) / 8;
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debug("SPI Rx unaligned: 0x%x\n", data);
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if (din) {
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for (i = 0; i < cnt; i++, data >>= 8) {
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*din++ = data & 0xFF;
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}
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}
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nbytes -= cnt;
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}
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while (nbytes > 0) {
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u32 tmp;
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tmp = reg_read(mxcs->base + MXC_CSPIRXDATA);
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data = cpu_to_be32(tmp);
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debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
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cnt = min(nbytes, sizeof(data));
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if (din) {
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memcpy(din, &data, cnt);
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din += cnt;
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}
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nbytes -= cnt;
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}
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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int n_bytes = (bitlen + 7) / 8;
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int n_bits;
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int ret;
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u32 blk_size;
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u8 *p_outbuf = (u8 *)dout;
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u8 *p_inbuf = (u8 *)din;
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if (!slave)
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return -1;
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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while (n_bytes > 0) {
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if (n_bytes < MAX_SPI_BYTES)
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blk_size = n_bytes;
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else
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blk_size = MAX_SPI_BYTES;
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n_bits = blk_size * 8;
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ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
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if (ret)
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return ret;
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if (dout)
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p_outbuf += blk_size;
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if (din)
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p_inbuf += blk_size;
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n_bytes -= blk_size;
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}
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if (flags & SPI_XFER_END) {
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spi_cs_deactivate(slave);
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}
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return 0;
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}
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void spi_init(void)
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{
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}
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static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
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{
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int ret;
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/*
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* Some SPI devices require active chip-select over multiple
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* transactions, we achieve this using a GPIO. Still, the SPI
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* controller has to be configured to use one of its own chipselects.
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* To use this feature you have to call spi_setup_slave() with
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* cs = internal_cs | (gpio << 8), and you have to use some unused
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* on this SPI controller cs between 0 and 3.
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*/
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if (cs > 3) {
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mxcs->gpio = cs >> 8;
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cs &= 3;
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ret = mxc_gpio_direction(mxcs->gpio, OUT);
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if (ret) {
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printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
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return -EINVAL;
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}
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} else {
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mxcs->gpio = -1;
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}
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return cs;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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unsigned int ctrl_reg;
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struct mxc_spi_slave *mxcs;
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int ret;
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if (bus >= ARRAY_SIZE(spi_bases))
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return NULL;
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mxcs = malloc(sizeof(struct mxc_spi_slave));
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if (!mxcs) {
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puts("mxc_spi: SPI Slave not allocated !\n");
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return NULL;
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}
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ret = decode_cs(mxcs, cs);
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if (ret < 0) {
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free(mxcs);
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return NULL;
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}
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cs = ret;
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mxcs->slave.bus = bus;
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mxcs->slave.cs = cs;
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mxcs->base = spi_bases[bus];
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mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
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#ifdef CONFIG_MX51
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/* Can be used for i.MX31 too ? */
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ctrl_reg = 0;
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ret = spi_cfg(mxcs, cs, max_hz, mode);
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if (ret) {
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printf("mxc_spi: cannot setup SPI controller\n");
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free(mxcs);
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return NULL;
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}
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#else
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(31) |
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MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
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MXC_CSPICTRL_EN |
|
|
MXC_CSPICTRL_MODE;
|
|
|
|
if (mode & SPI_CPHA)
|
|
ctrl_reg |= MXC_CSPICTRL_PHA;
|
|
if (mode & SPI_CPOL)
|
|
ctrl_reg |= MXC_CSPICTRL_POL;
|
|
if (mode & SPI_CS_HIGH)
|
|
ctrl_reg |= MXC_CSPICTRL_SSPOL;
|
|
mxcs->ctrl_reg = ctrl_reg;
|
|
#endif
|
|
return &mxcs->slave;
|
|
}
|
|
|
|
void spi_free_slave(struct spi_slave *slave)
|
|
{
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
|
|
free(mxcs);
|
|
}
|
|
|
|
int spi_claim_bus(struct spi_slave *slave)
|
|
{
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
|
|
reg_write(mxcs->base + MXC_CSPIRESET, 1);
|
|
udelay(1);
|
|
reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
|
|
reg_write(mxcs->base + MXC_CSPIPERIOD,
|
|
MXC_CSPIPERIOD_32KHZ);
|
|
reg_write(mxcs->base + MXC_CSPIINT, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void spi_release_bus(struct spi_slave *slave)
|
|
{
|
|
/* TODO: Shut the controller down */
|
|
}
|